1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/clock/stm32mp13-clksrc.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/stm32mp13-resets.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-a7";
22			device_type = "cpu";
23			reg = <0>;
24		};
25	};
26
27	intc: interrupt-controller@a0021000 {
28		compatible = "arm,cortex-a7-gic";
29		#interrupt-cells = <3>;
30		interrupt-controller;
31		reg = <0xa0021000 0x1000>,
32		      <0xa0022000 0x2000>;
33	};
34
35	psci {
36		compatible = "arm,psci-1.0";
37		method = "smc";
38	};
39
40	clocks {
41		clk_hse: clk-hse {
42			#clock-cells = <0>;
43			compatible = "fixed-clock";
44			clock-frequency = <24000000>;
45		};
46
47		clk_hsi: clk-hsi {
48			#clock-cells = <0>;
49			compatible = "fixed-clock";
50			clock-frequency = <64000000>;
51		};
52
53		clk_lse: clk-lse {
54			#clock-cells = <0>;
55			compatible = "fixed-clock";
56			clock-frequency = <32768>;
57		};
58
59		clk_lsi: clk-lsi {
60			#clock-cells = <0>;
61			compatible = "fixed-clock";
62			clock-frequency = <32000>;
63		};
64
65		clk_csi: clk-csi {
66			#clock-cells = <0>;
67			compatible = "fixed-clock";
68			clock-frequency = <4000000>;
69		};
70
71		clk_i2sin: clk-i2sin {
72			#clock-cells = <0>;
73			compatible = "fixed-clock";
74			clock-frequency = <19000000>;
75		};
76
77	};
78
79	soc {
80		compatible = "simple-bus";
81		#address-cells = <1>;
82		#size-cells = <1>;
83		interrupt-parent = <&intc>;
84		ranges;
85
86		usart3: serial@4000f000 {
87			compatible = "st,stm32h7-uart";
88			reg = <0x4000f000 0x400>;
89			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
90			status = "disabled";
91		};
92
93		uart4: serial@40010000 {
94			compatible = "st,stm32h7-uart";
95			reg = <0x40010000 0x400>;
96			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
97			clocks = <&rcc UART4_K>;
98			status = "disabled";
99		};
100
101		uart5: serial@40011000 {
102			compatible = "st,stm32h7-uart";
103			reg = <0x40011000 0x400>;
104			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
105			status = "disabled";
106		};
107
108		uart7: serial@40018000 {
109			compatible = "st,stm32h7-uart";
110			reg = <0x40018000 0x400>;
111			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112			status = "disabled";
113		};
114
115		uart8: serial@40019000 {
116			compatible = "st,stm32h7-uart";
117			reg = <0x40019000 0x400>;
118			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
119			status = "disabled";
120		};
121
122		usart6: serial@44003000 {
123			compatible = "st,stm32h7-uart";
124			reg = <0x44003000 0x400>;
125			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
126			status = "disabled";
127		};
128
129		usart1: serial@4c000000 {
130			compatible = "st,stm32h7-uart";
131			reg = <0x4c000000 0x400>;
132			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
133			status = "disabled";
134		};
135
136		usart2: serial@4c001000 {
137			compatible = "st,stm32h7-uart";
138			reg = <0x4c001000 0x400>;
139			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
140			status = "disabled";
141		};
142
143		i2c3: i2c@4c004000 {
144			compatible = "st,stm32mp13-i2c";
145			reg = <0x4c004000 0x400>;
146			#address-cells = <1>;
147			#size-cells = <0>;
148			st,syscfg-fmp = <&syscfg 0x4 0x4>;
149			i2c-analog-filter;
150			status = "disabled";
151		};
152
153		i2c4: i2c@4c005000 {
154			compatible = "st,stm32mp13-i2c";
155			reg = <0x4c005000 0x400>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158			st,syscfg-fmp = <&syscfg 0x4 0x8>;
159			i2c-analog-filter;
160			status = "disabled";
161		};
162
163		i2c5: i2c@4c006000 {
164			compatible = "st,stm32mp13-i2c";
165			reg = <0x4c006000 0x400>;
166			#address-cells = <1>;
167			#size-cells = <0>;
168			st,syscfg-fmp = <&syscfg 0x4 0x10>;
169			i2c-analog-filter;
170			status = "disabled";
171		};
172
173		rcc: rcc@50000000 {
174			compatible = "st,stm32mp13-rcc", "syscon";
175			reg = <0x50000000 0x1000>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			#clock-cells = <1>;
179			#reset-cells = <1>;
180			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>;
181			clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin";
182			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
183			secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
184			secure-interrupt-names = "wakeup";
185		};
186
187		syscfg: syscon@50020000 {
188			compatible = "st,stm32mp157-syscfg", "syscon";
189			reg = <0x50020000 0x400>;
190		};
191
192		bsec: efuse@5c005000 {
193			compatible = "st,stm32mp13-bsec";
194			reg = <0x5c005000 0x400>;
195			#address-cells = <1>;
196			#size-cells = <1>;
197
198			cfg0_otp: cfg0_otp@0 {
199				reg = <0x0 0x2>;
200			};
201			part_number_otp: part_number_otp@4 {
202				reg = <0x4 0x2>;
203			};
204			monotonic_otp: monotonic_otp@10 {
205				reg = <0x10 0x4>;
206			};
207			nand_otp: cfg9_otp@24 {
208				reg = <0x24 0x4>;
209			};
210			uid_otp: uid_otp@34 {
211				reg = <0x34 0xc>;
212			};
213			hw2_otp: hw2_otp@48 {
214				reg = <0x48 0x4>;
215			};
216			ts_cal1: calib@5c {
217				reg = <0x5c 0x2>;
218			};
219			ts_cal2: calib@5e {
220				reg = <0x5e 0x2>;
221			};
222			pkh_otp: pkh_otp@60 {
223				reg = <0x60 0x20>;
224			};
225			ethernet_mac1_address: mac1@e4 {
226				reg = <0xe4 0xc>;
227				st,non-secure-otp;
228			};
229			oem_enc_key: oem_enc_key@170 {
230				reg = <0x170 0x10>;
231			};
232		};
233
234		tzc400: tzc@5c006000 {
235			compatible = "st,stm32mp1-tzc";
236			reg = <0x5c006000 0x1000>;
237			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
238			st,mem-map = <0xc0000000 0x40000000>;
239			clocks = <&rcc TZC>;
240		};
241
242		etzpc: etzpc@5c007000 {
243			compatible = "st,stm32-etzpc";
244			reg = <0x5C007000 0x400>;
245		};
246
247		stgen: stgen@5c008000 {
248			compatible = "st,stm32-stgen";
249			reg = <0x5C008000 0x1000>;
250		};
251
252		pinctrl: pin-controller@50002000 {
253			#address-cells = <1>;
254			#size-cells = <1>;
255			compatible = "st,stm32mp135-pinctrl";
256			ranges = <0 0x50002000 0x8400>;
257			pins-are-numbered;
258
259			gpioa: gpio@50002000 {
260				gpio-controller;
261				#gpio-cells = <2>;
262				interrupt-controller;
263				#interrupt-cells = <2>;
264				clocks = <&rcc GPIOA>;
265				reg = <0x0 0x400>;
266				st,bank-name = "GPIOA";
267				ngpios = <16>;
268				gpio-ranges = <&pinctrl 0 0 16>;
269			};
270
271			gpiob: gpio@50003000 {
272				gpio-controller;
273				#gpio-cells = <2>;
274				interrupt-controller;
275				#interrupt-cells = <2>;
276				clocks = <&rcc GPIOB>;
277				reg = <0x1000 0x400>;
278				st,bank-name = "GPIOB";
279				ngpios = <16>;
280				gpio-ranges = <&pinctrl 0 16 16>;
281			};
282
283			gpioc: gpio@50004000 {
284				gpio-controller;
285				#gpio-cells = <2>;
286				interrupt-controller;
287				#interrupt-cells = <2>;
288				clocks = <&rcc GPIOC>;
289				reg = <0x2000 0x400>;
290				st,bank-name = "GPIOC";
291				ngpios = <16>;
292				gpio-ranges = <&pinctrl 0 32 16>;
293			};
294
295			gpiod: gpio@50005000 {
296				gpio-controller;
297				#gpio-cells = <2>;
298				interrupt-controller;
299				#interrupt-cells = <2>;
300				clocks = <&rcc GPIOD>;
301				reg = <0x3000 0x400>;
302				st,bank-name = "GPIOD";
303				ngpios = <16>;
304				gpio-ranges = <&pinctrl 0 48 16>;
305			};
306
307			gpioe: gpio@50006000 {
308				gpio-controller;
309				#gpio-cells = <2>;
310				interrupt-controller;
311				#interrupt-cells = <2>;
312				clocks = <&rcc GPIOE>;
313				reg = <0x4000 0x400>;
314				st,bank-name = "GPIOE";
315				ngpios = <16>;
316				gpio-ranges = <&pinctrl 0 64 16>;
317			};
318
319			gpiof: gpio@50007000 {
320				gpio-controller;
321				#gpio-cells = <2>;
322				interrupt-controller;
323				#interrupt-cells = <2>;
324				clocks = <&rcc GPIOF>;
325				reg = <0x5000 0x400>;
326				st,bank-name = "GPIOF";
327				ngpios = <16>;
328				gpio-ranges = <&pinctrl 0 80 16>;
329			};
330
331			gpiog: gpio@50008000 {
332				gpio-controller;
333				#gpio-cells = <2>;
334				interrupt-controller;
335				#interrupt-cells = <2>;
336				clocks = <&rcc GPIOG>;
337				reg = <0x6000 0x400>;
338				st,bank-name = "GPIOG";
339				ngpios = <16>;
340				gpio-ranges = <&pinctrl 0 96 16>;
341			};
342
343			gpioh: gpio@50009000 {
344				gpio-controller;
345				#gpio-cells = <2>;
346				interrupt-controller;
347				#interrupt-cells = <2>;
348				clocks = <&rcc GPIOH>;
349				reg = <0x7000 0x400>;
350				st,bank-name = "GPIOH";
351				ngpios = <15>;
352				gpio-ranges = <&pinctrl 0 112 15>;
353			};
354
355			gpioi: gpio@5000a000 {
356				gpio-controller;
357				#gpio-cells = <2>;
358				interrupt-controller;
359				#interrupt-cells = <2>;
360				clocks = <&rcc GPIOI>;
361				reg = <0x8000 0x400>;
362				st,bank-name = "GPIOI";
363				ngpios = <8>;
364				gpio-ranges = <&pinctrl 0 128 8>;
365			};
366		};
367	};
368};
369