1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/clock/stm32mp13-clksrc.h>
10#include "stm32mp135.dtsi"
11#include "stm32mp13xf.dtsi"
12#include "stm32mp13-pinctrl.dtsi"
13
14/ {
15	model = "STMicroelectronics STM32MP135F-DK Discovery Board";
16	compatible = "st,stm32mp135f-dk", "st,stm32mp135";
17
18	aliases {
19		serial0 = &uart4;
20		serial1 = &usart1;
21	};
22
23	chosen {
24		stdout-path = "serial0:115200n8";
25	};
26
27	memory@c0000000 {
28		device_type = "memory";
29		reg = <0xc0000000 0x20000000>;
30	};
31
32        reserved-memory {
33                #address-cells = <1>;
34                #size-cells = <1>;
35                ranges;
36
37                optee_framebuffer: optee-framebuffer@dd000000 {
38                        /* Secure framebuffer memory */
39                        reg = <0xdd000000 0x1000000>;
40                        no-map;
41                };
42        };
43
44	vin: vin {
45		compatible = "regulator-fixed";
46		regulator-name = "vin";
47		regulator-min-microvolt = <5000000>;
48		regulator-max-microvolt = <5000000>;
49		regulator-always-on;
50	};
51
52	v3v3_ao: v3v3_ao {
53		compatible = "regulator-fixed";
54		regulator-name = "v3v3_ao";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		regulator-always-on;
58	};
59};
60
61&bsec {
62	board_id: board_id@f0 {
63		reg = <0xf0 0x4>;
64		st,non-secure-otp;
65	};
66};
67
68&oem_enc_key {
69	st,non-secure-otp-provisioning;
70};
71
72&rcc {
73	compatible = "st,stm32mp13-rcc", "syscon";
74
75	st,clksrc = <
76		CLK_MPU_PLL1P
77		CLK_AXI_PLL2P
78		CLK_MLAHBS_PLL3
79		CLK_RTC_LSE
80		CLK_MCO1_HSE
81		CLK_MCO2_DISABLED
82		CLK_CKPER_HSE
83		CLK_ETH1_PLL4P
84		CLK_ETH2_PLL4P
85		CLK_SDMMC1_PLL4P
86		CLK_SDMMC2_PLL4P
87		CLK_STGEN_HSE
88		CLK_USBPHY_HSE
89		CLK_I2C4_HSI
90		CLK_USBO_USBPHY
91		CLK_ADC2_CKPER
92		CLK_I2C12_HSI
93		CLK_UART1_HSI
94		CLK_UART2_HSI
95		CLK_UART35_HSI
96		CLK_UART4_HSI
97		CLK_UART6_HSI
98		CLK_UART78_HSI
99		CLK_SAES_AXI
100		CLK_DCMIPP_PLL2Q
101		CLK_LPTIM3_PCLK3
102		CLK_RNG1_PLL4R
103	>;
104
105	st,clkdiv = <
106		DIV(DIV_MPU, 1)
107		DIV(DIV_AXI, 0)
108		DIV(DIV_MLAHB, 0)
109		DIV(DIV_APB1, 1)
110		DIV(DIV_APB2, 1)
111		DIV(DIV_APB3, 1)
112		DIV(DIV_APB4, 1)
113		DIV(DIV_APB5, 2)
114		DIV(DIV_APB6, 1)
115		DIV(DIV_RTC, 0)
116		DIV(DIV_MCO1, 0)
117		DIV(DIV_MCO2, 0)
118	>;
119
120	st,pll_vco {
121		pll1_vco_2000Mhz: pll1-vco-2000Mhz {
122			src = < CLK_PLL12_HSE >;
123			divmn = < 1 82 >;
124			frac = < 0xAAA >;
125		};
126
127		pll1_vco_1300Mhz: pll1-vco-1300Mhz {
128			src = < CLK_PLL12_HSE >;
129			divmn = < 2 80 >;
130			frac = < 0x800 >;
131		};
132
133		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
134			src = < CLK_PLL12_HSE >;
135			divmn = < 2 65 >;
136			frac = < 0x1400 >;
137		};
138
139		pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
140			src = < CLK_PLL3_HSE >;
141			divmn = < 1 33 >;
142			frac = < 0x1a04 >;
143		};
144
145		pll4_vco_600Mhz: pll4-vco-600Mhz {
146			src = < CLK_PLL4_HSE >;
147			divmn = < 1 49 >;
148		};
149	};
150
151	/* VCO = 1300.0 MHz => P = 650 (CPU) */
152	pll1: st,pll@0 {
153		compatible = "st,stm32mp1-pll";
154		reg = <0>;
155
156		st,pll = < &pll1_cfg1 >;
157
158		pll1_cfg1: pll1_cfg1 {
159			st,pll_vco = < &pll1_vco_1300Mhz >;
160			st,pll_div_pqr = < 0 1 1 >;
161		};
162
163		pll1_cfg2: pll1_cfg2 {
164			st,pll_vco = < &pll1_vco_2000Mhz >;
165			st,pll_div_pqr = < 0 1 1 >;
166		};
167	};
168
169	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
170	pll2: st,pll@1 {
171		compatible = "st,stm32mp1-pll";
172		reg = <1>;
173
174		st,pll = < &pll2_cfg1 >;
175
176		pll2_cfg1: pll2_cfg1 {
177			st,pll_vco = < &pll2_vco_1066Mhz >;
178			st,pll_div_pqr = < 1 1 0 >;
179		};
180	};
181
182	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
183	pll3: st,pll@2 {
184		compatible = "st,stm32mp1-pll";
185		reg = <2>;
186
187		st,pll = < &pll3_cfg1 >;
188
189		pll3_cfg1: pll3_cfg1 {
190			st,pll_vco = < &pll3_vco_417_8Mhz >;
191			st,pll_div_pqr = < 1 16 36 >;
192		};
193	};
194
195	/* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */
196	pll4: st,pll@3 {
197		compatible = "st,stm32mp1-pll";
198		reg = <3>;
199		st,pll = < &pll4_cfg1 >;
200
201		pll4_cfg1: pll4_cfg1 {
202			st,pll_vco = < &pll4_vco_600Mhz >;
203			st,pll_div_pqr = < 11 59 11 >;
204		};
205	};
206
207	st,clk_opp {
208		/* CK_MPU clock config for MP13 */
209		st,ck_mpu {
210
211			cfg_1 {
212				hz = < 1000000000 >;
213				st,clksrc = < CLK_MPU_PLL1P >;
214				st,pll = < &pll1_cfg2 >;
215			};
216
217			cfg_2 {
218				hz = < 650000000 >;
219				st,clksrc = < CLK_MPU_PLL1P >;
220				st,pll = < &pll1_cfg1 >;
221			};
222		};
223	};
224};
225
226&uart4 {
227	pinctrl-names = "default";
228	pinctrl-0 = <&uart4_pins_a>;
229	status = "okay";
230};
231
232&usart1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&usart1_pins_a>;
235	uart-has-rtscts;
236	status = "disabled";
237};
238
239&uart8 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&uart8_pins_a>;
242	status = "disabled";
243};
244