1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 adc1_in6_pins_a: adc1-in6-0 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_ain_pins_b: adc12-ain-1 { 25 pins { 26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ 28 }; 29 }; 30 31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 35 }; 36 }; 37 38 cec_pins_a: cec-0 { 39 pins { 40 pinmux = <STM32_PINMUX('A', 15, AF4)>; 41 bias-disable; 42 drive-open-drain; 43 slew-rate = <0>; 44 }; 45 }; 46 47 cec_sleep_pins_a: cec-sleep-0 { 48 pins { 49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 50 }; 51 }; 52 53 cec_pins_b: cec-1 { 54 pins { 55 pinmux = <STM32_PINMUX('B', 6, AF5)>; 56 bias-disable; 57 drive-open-drain; 58 slew-rate = <0>; 59 }; 60 }; 61 62 cec_sleep_pins_b: cec-sleep-1 { 63 pins { 64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 65 }; 66 }; 67 68 dac_ch1_pins_a: dac-ch1-0 { 69 pins { 70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 71 }; 72 }; 73 74 dac_ch2_pins_a: dac-ch2-0 { 75 pins { 76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 77 }; 78 }; 79 80 dcmi_pins_a: dcmi-0 { 81 pins { 82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 97 bias-disable; 98 }; 99 }; 100 101 dcmi_sleep_pins_a: dcmi-sleep-0 { 102 pins { 103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 118 }; 119 }; 120 121 dcmi_pins_b: dcmi-1 { 122 pins { 123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 124 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 126 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ 127 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 128 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 130 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ 131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 132 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ 133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ 134 bias-disable; 135 }; 136 }; 137 138 dcmi_sleep_pins_b: dcmi-sleep-1 { 139 pins { 140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 141 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 143 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ 144 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 145 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 147 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ 148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 149 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ 150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ 151 }; 152 }; 153 154 ethernet0_rgmii_pins_a: rgmii-0 { 155 pins1 { 156 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 157 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 158 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 159 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 160 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 161 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 162 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 163 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 164 bias-disable; 165 drive-push-pull; 166 slew-rate = <2>; 167 }; 168 pins2 { 169 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 170 bias-disable; 171 drive-push-pull; 172 slew-rate = <0>; 173 }; 174 pins3 { 175 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 176 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 177 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 178 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 179 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 180 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 181 bias-disable; 182 }; 183 }; 184 185 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { 186 pins1 { 187 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 188 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 189 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 190 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 191 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 192 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 193 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 194 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 195 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 196 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 197 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 198 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 199 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 200 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 201 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 202 }; 203 }; 204 205 ethernet0_rgmii_pins_b: rgmii-1 { 206 pins1 { 207 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 208 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 209 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 210 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 211 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 212 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 213 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 214 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 215 bias-disable; 216 drive-push-pull; 217 slew-rate = <2>; 218 }; 219 pins2 { 220 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 221 bias-disable; 222 drive-push-pull; 223 slew-rate = <0>; 224 }; 225 pins3 { 226 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 227 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 228 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 229 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 230 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 231 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 232 bias-disable; 233 }; 234 }; 235 236 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { 237 pins1 { 238 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 239 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 240 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 241 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 242 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 243 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 244 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 245 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 246 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 247 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 248 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 249 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 250 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 251 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 252 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 253 }; 254 }; 255 256 ethernet0_rgmii_pins_c: rgmii-2 { 257 pins1 { 258 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 259 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 260 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 261 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 262 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 263 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 264 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 265 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 266 bias-disable; 267 drive-push-pull; 268 slew-rate = <2>; 269 }; 270 pins2 { 271 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 272 bias-disable; 273 drive-push-pull; 274 slew-rate = <0>; 275 }; 276 pins3 { 277 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 278 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 279 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 280 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 281 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 282 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 283 bias-disable; 284 }; 285 }; 286 287 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { 288 pins1 { 289 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 290 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 291 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 292 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 293 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 294 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 295 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 296 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 297 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 298 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 299 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 300 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 301 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 302 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 303 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 304 }; 305 }; 306 307 ethernet0_rmii_pins_a: rmii-0 { 308 pins1 { 309 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 310 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 311 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 312 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ 313 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 314 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 315 bias-disable; 316 drive-push-pull; 317 slew-rate = <2>; 318 }; 319 pins2 { 320 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 321 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 322 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 323 bias-disable; 324 }; 325 }; 326 327 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { 328 pins1 { 329 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 330 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 331 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 332 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 333 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 334 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 335 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 336 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 337 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 338 }; 339 }; 340 341 ethernet0_rmii_pins_b: rmii-1 { 342 pins1 { 343 pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ 344 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ 345 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ 346 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ 347 bias-disable; 348 drive-push-pull; 349 slew-rate = <1>; 350 }; 351 pins2 { 352 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ 353 bias-disable; 354 drive-push-pull; 355 slew-rate = <0>; 356 }; 357 pins3 { 358 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ 359 <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ 360 <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ 361 bias-disable; 362 }; 363 pins4 { 364 pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ 365 }; 366 }; 367 368 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { 369 pins1 { 370 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 371 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ 372 <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ 373 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ 374 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 375 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ 376 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ 377 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ 378 <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ 379 }; 380 }; 381 382 ethernet0_rmii_pins_c: rmii-2 { 383 pins1 { 384 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 385 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 386 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 387 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ 388 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 389 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 390 bias-disable; 391 drive-push-pull; 392 slew-rate = <2>; 393 }; 394 pins2 { 395 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 396 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 397 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 398 bias-disable; 399 }; 400 }; 401 402 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { 403 pins1 { 404 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 405 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 406 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 407 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 408 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 409 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 410 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 411 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 412 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 413 }; 414 }; 415 416 fmc_pins_a: fmc-0 { 417 pins1 { 418 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 419 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 420 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 421 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 422 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 423 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 424 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 425 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 426 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 427 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 428 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 429 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 430 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 431 bias-disable; 432 drive-push-pull; 433 slew-rate = <1>; 434 }; 435 pins2 { 436 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 437 bias-pull-up; 438 }; 439 }; 440 441 fmc_sleep_pins_a: fmc-sleep-0 { 442 pins { 443 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 444 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 445 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 446 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 447 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 448 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 449 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 450 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 451 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 452 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 453 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 454 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 455 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 456 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 457 }; 458 }; 459 460 fmc_pins_b: fmc-1 { 461 pins { 462 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 463 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 464 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ 465 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 466 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 467 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 468 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 469 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 470 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 471 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 472 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 473 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ 474 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ 475 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ 476 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ 477 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ 478 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ 479 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ 480 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ 481 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ 482 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ 483 bias-disable; 484 drive-push-pull; 485 slew-rate = <3>; 486 }; 487 }; 488 489 fmc_sleep_pins_b: fmc-sleep-1 { 490 pins { 491 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 492 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 493 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ 494 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 495 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 496 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 497 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 498 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 499 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 500 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 501 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 502 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ 503 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ 504 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ 505 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ 506 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ 507 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ 508 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ 509 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ 510 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ 511 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ 512 }; 513 }; 514 515 i2c1_pins_a: i2c1-0 { 516 pins { 517 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 518 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 519 bias-disable; 520 drive-open-drain; 521 slew-rate = <0>; 522 }; 523 }; 524 525 i2c1_sleep_pins_a: i2c1-sleep-0 { 526 pins { 527 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 528 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 529 }; 530 }; 531 532 i2c1_pins_b: i2c1-1 { 533 pins { 534 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 535 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 536 bias-disable; 537 drive-open-drain; 538 slew-rate = <0>; 539 }; 540 }; 541 542 i2c1_sleep_pins_b: i2c1-sleep-1 { 543 pins { 544 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 545 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 546 }; 547 }; 548 549 i2c2_pins_a: i2c2-0 { 550 pins { 551 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 552 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 553 bias-disable; 554 drive-open-drain; 555 slew-rate = <0>; 556 }; 557 }; 558 559 i2c2_sleep_pins_a: i2c2-sleep-0 { 560 pins { 561 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 562 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 563 }; 564 }; 565 566 i2c2_pins_b1: i2c2-1 { 567 pins { 568 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 569 bias-disable; 570 drive-open-drain; 571 slew-rate = <0>; 572 }; 573 }; 574 575 i2c2_sleep_pins_b1: i2c2-sleep-1 { 576 pins { 577 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 578 }; 579 }; 580 581 i2c2_pins_c: i2c2-2 { 582 pins { 583 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ 584 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 585 bias-disable; 586 drive-open-drain; 587 slew-rate = <0>; 588 }; 589 }; 590 591 i2c2_pins_sleep_c: i2c2-sleep-2 { 592 pins { 593 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ 594 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 595 }; 596 }; 597 598 i2c5_pins_a: i2c5-0 { 599 pins { 600 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 601 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 602 bias-disable; 603 drive-open-drain; 604 slew-rate = <0>; 605 }; 606 }; 607 608 i2c5_sleep_pins_a: i2c5-sleep-0 { 609 pins { 610 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 611 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 612 613 }; 614 }; 615 616 i2c5_pins_b: i2c5-1 { 617 pins { 618 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ 619 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ 620 bias-disable; 621 drive-open-drain; 622 slew-rate = <0>; 623 }; 624 }; 625 626 i2c5_sleep_pins_b: i2c5-sleep-1 { 627 pins { 628 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ 629 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ 630 }; 631 }; 632 633 i2s2_pins_a: i2s2-0 { 634 pins { 635 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 636 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 637 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 638 slew-rate = <1>; 639 drive-push-pull; 640 bias-disable; 641 }; 642 }; 643 644 i2s2_sleep_pins_a: i2s2-sleep-0 { 645 pins { 646 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 647 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 648 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 649 }; 650 }; 651 652 ltdc_pins_a: ltdc-0 { 653 pins { 654 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 655 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 656 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 657 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 658 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 659 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 660 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 661 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 662 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 663 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 664 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 665 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 666 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 667 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 668 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 669 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 670 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 671 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 672 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 673 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 674 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 675 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 676 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 677 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 678 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 679 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 680 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 681 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 682 bias-disable; 683 drive-push-pull; 684 slew-rate = <1>; 685 }; 686 }; 687 688 ltdc_sleep_pins_a: ltdc-sleep-0 { 689 pins { 690 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 691 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 692 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 693 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 694 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 695 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 696 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 697 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 698 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 699 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 700 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 701 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 702 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 703 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 704 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 705 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 706 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 707 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 708 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 709 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 710 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 711 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 712 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 713 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 714 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 715 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 716 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 717 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 718 }; 719 }; 720 721 ltdc_pins_b: ltdc-1 { 722 pins { 723 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 724 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 725 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 726 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 727 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 728 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 729 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 730 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 731 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 732 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 733 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 734 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 735 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 736 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 737 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 738 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 739 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 740 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 741 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 742 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 743 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 744 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 745 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 746 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 747 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 748 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 749 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 750 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 751 bias-disable; 752 drive-push-pull; 753 slew-rate = <1>; 754 }; 755 }; 756 757 ltdc_sleep_pins_b: ltdc-sleep-1 { 758 pins { 759 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 760 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 761 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 762 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 763 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 764 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 765 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 766 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 767 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 768 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 769 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 770 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 771 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 772 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 773 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 774 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 775 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 776 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 777 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 778 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 779 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 780 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 781 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 782 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 783 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 784 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 785 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 786 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 787 }; 788 }; 789 790 ltdc_pins_c: ltdc-2 { 791 pins1 { 792 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ 793 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ 794 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ 795 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ 796 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ 797 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ 798 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ 799 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ 800 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ 801 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ 802 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ 803 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ 804 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ 805 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ 806 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ 807 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ 808 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ 809 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ 810 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ 811 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ 812 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ 813 bias-disable; 814 drive-push-pull; 815 slew-rate = <0>; 816 }; 817 pins2 { 818 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ 819 bias-disable; 820 drive-push-pull; 821 slew-rate = <1>; 822 }; 823 }; 824 825 ltdc_sleep_pins_c: ltdc-sleep-2 { 826 pins1 { 827 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ 828 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ 829 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ 830 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ 831 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ 832 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ 833 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ 834 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ 835 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ 836 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ 837 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ 838 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ 839 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ 840 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ 841 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ 842 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ 843 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ 844 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ 845 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ 846 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ 847 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ 848 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ 849 }; 850 }; 851 852 ltdc_pins_d: ltdc-3 { 853 pins1 { 854 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ 855 bias-disable; 856 drive-push-pull; 857 slew-rate = <3>; 858 }; 859 pins2 { 860 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 861 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 862 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ 863 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ 864 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 865 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 866 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 867 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ 868 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ 869 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 870 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 871 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 872 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ 873 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 874 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ 875 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 876 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ 877 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ 878 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ 879 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 880 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 881 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 882 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 883 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ 884 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 885 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 886 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ 887 bias-disable; 888 drive-push-pull; 889 slew-rate = <2>; 890 }; 891 }; 892 893 ltdc_sleep_pins_d: ltdc-sleep-3 { 894 pins { 895 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 896 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 897 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 898 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ 899 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ 900 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 901 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 902 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 903 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ 904 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ 905 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 906 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 907 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 908 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ 909 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 910 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ 911 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 912 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ 913 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ 914 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ 915 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 916 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 917 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 918 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 919 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ 920 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 921 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 922 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ 923 }; 924 }; 925 926 mco2_pins_a: mco2-0 { 927 pins { 928 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ 929 bias-disable; 930 drive-push-pull; 931 slew-rate = <2>; 932 }; 933 }; 934 935 mco2_sleep_pins_a: mco2-sleep-0 { 936 pins { 937 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ 938 }; 939 }; 940 941 m_can1_pins_a: m-can1-0 { 942 pins1 { 943 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 944 slew-rate = <1>; 945 drive-push-pull; 946 bias-disable; 947 }; 948 pins2 { 949 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 950 bias-disable; 951 }; 952 }; 953 954 m_can1_sleep_pins_a: m_can1-sleep-0 { 955 pins { 956 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 957 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 958 }; 959 }; 960 961 m_can1_pins_b: m-can1-1 { 962 pins1 { 963 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 964 slew-rate = <1>; 965 drive-push-pull; 966 bias-disable; 967 }; 968 pins2 { 969 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 970 bias-disable; 971 }; 972 }; 973 974 m_can1_sleep_pins_b: m_can1-sleep-1 { 975 pins { 976 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ 977 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ 978 }; 979 }; 980 981 m_can2_pins_a: m-can2-0 { 982 pins1 { 983 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 984 slew-rate = <1>; 985 drive-push-pull; 986 bias-disable; 987 }; 988 pins2 { 989 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 990 bias-disable; 991 }; 992 }; 993 994 m_can2_sleep_pins_a: m_can2-sleep-0 { 995 pins { 996 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ 997 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ 998 }; 999 }; 1000 1001 pwm1_pins_a: pwm1-0 { 1002 pins { 1003 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 1004 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 1005 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 1006 bias-pull-down; 1007 drive-push-pull; 1008 slew-rate = <0>; 1009 }; 1010 }; 1011 1012 pwm1_sleep_pins_a: pwm1-sleep-0 { 1013 pins { 1014 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 1015 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 1016 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 1017 }; 1018 }; 1019 1020 pwm1_pins_b: pwm1-1 { 1021 pins { 1022 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ 1023 bias-pull-down; 1024 drive-push-pull; 1025 slew-rate = <0>; 1026 }; 1027 }; 1028 1029 pwm1_sleep_pins_b: pwm1-sleep-1 { 1030 pins { 1031 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ 1032 }; 1033 }; 1034 1035 pwm2_pins_a: pwm2-0 { 1036 pins { 1037 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 1038 bias-pull-down; 1039 drive-push-pull; 1040 slew-rate = <0>; 1041 }; 1042 }; 1043 1044 pwm2_sleep_pins_a: pwm2-sleep-0 { 1045 pins { 1046 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 1047 }; 1048 }; 1049 1050 pwm3_pins_a: pwm3-0 { 1051 pins { 1052 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 1053 bias-pull-down; 1054 drive-push-pull; 1055 slew-rate = <0>; 1056 }; 1057 }; 1058 1059 pwm3_sleep_pins_a: pwm3-sleep-0 { 1060 pins { 1061 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 1062 }; 1063 }; 1064 1065 pwm3_pins_b: pwm3-1 { 1066 pins { 1067 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 1068 bias-disable; 1069 drive-push-pull; 1070 slew-rate = <0>; 1071 }; 1072 }; 1073 1074 pwm3_sleep_pins_b: pwm3-sleep-1 { 1075 pins { 1076 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ 1077 }; 1078 }; 1079 1080 pwm4_pins_a: pwm4-0 { 1081 pins { 1082 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 1083 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 1084 bias-pull-down; 1085 drive-push-pull; 1086 slew-rate = <0>; 1087 }; 1088 }; 1089 1090 pwm4_sleep_pins_a: pwm4-sleep-0 { 1091 pins { 1092 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 1093 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 1094 }; 1095 }; 1096 1097 pwm4_pins_b: pwm4-1 { 1098 pins { 1099 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 1100 bias-pull-down; 1101 drive-push-pull; 1102 slew-rate = <0>; 1103 }; 1104 }; 1105 1106 pwm4_sleep_pins_b: pwm4-sleep-1 { 1107 pins { 1108 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 1109 }; 1110 }; 1111 1112 pwm5_pins_a: pwm5-0 { 1113 pins { 1114 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 1115 bias-pull-down; 1116 drive-push-pull; 1117 slew-rate = <0>; 1118 }; 1119 }; 1120 1121 pwm5_sleep_pins_a: pwm5-sleep-0 { 1122 pins { 1123 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 1124 }; 1125 }; 1126 1127 pwm5_pins_b: pwm5-1 { 1128 pins { 1129 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ 1130 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ 1131 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ 1132 bias-disable; 1133 drive-push-pull; 1134 slew-rate = <0>; 1135 }; 1136 }; 1137 1138 pwm5_sleep_pins_b: pwm5-sleep-1 { 1139 pins { 1140 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ 1141 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ 1142 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ 1143 }; 1144 }; 1145 1146 pwm8_pins_a: pwm8-0 { 1147 pins { 1148 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 1149 bias-pull-down; 1150 drive-push-pull; 1151 slew-rate = <0>; 1152 }; 1153 }; 1154 1155 pwm8_sleep_pins_a: pwm8-sleep-0 { 1156 pins { 1157 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 1158 }; 1159 }; 1160 1161 pwm12_pins_a: pwm12-0 { 1162 pins { 1163 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 1164 bias-pull-down; 1165 drive-push-pull; 1166 slew-rate = <0>; 1167 }; 1168 }; 1169 1170 pwm12_sleep_pins_a: pwm12-sleep-0 { 1171 pins { 1172 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 1173 }; 1174 }; 1175 1176 qspi_clk_pins_a: qspi-clk-0 { 1177 pins { 1178 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 1179 bias-disable; 1180 drive-push-pull; 1181 slew-rate = <3>; 1182 }; 1183 }; 1184 1185 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 1186 pins { 1187 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 1188 }; 1189 }; 1190 1191 qspi_bk1_pins_a: qspi-bk1-0 { 1192 pins1 { 1193 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 1194 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 1195 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 1196 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 1197 bias-disable; 1198 drive-push-pull; 1199 slew-rate = <1>; 1200 }; 1201 pins2 { 1202 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 1203 bias-pull-up; 1204 drive-push-pull; 1205 slew-rate = <1>; 1206 }; 1207 }; 1208 1209 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 1210 pins { 1211 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 1212 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 1213 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 1214 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ 1215 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 1216 }; 1217 }; 1218 1219 qspi_bk2_pins_a: qspi-bk2-0 { 1220 pins1 { 1221 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 1222 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 1223 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 1224 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 1225 bias-disable; 1226 drive-push-pull; 1227 slew-rate = <1>; 1228 }; 1229 pins2 { 1230 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 1231 bias-pull-up; 1232 drive-push-pull; 1233 slew-rate = <1>; 1234 }; 1235 }; 1236 1237 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 1238 pins { 1239 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 1240 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 1241 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 1242 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ 1243 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 1244 }; 1245 }; 1246 1247 sai2a_pins_a: sai2a-0 { 1248 pins { 1249 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 1250 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1251 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1252 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 1253 slew-rate = <0>; 1254 drive-push-pull; 1255 bias-disable; 1256 }; 1257 }; 1258 1259 sai2a_sleep_pins_a: sai2a-sleep-0 { 1260 pins { 1261 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 1262 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1263 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1264 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 1265 }; 1266 }; 1267 1268 sai2a_pins_b: sai2a-1 { 1269 pins1 { 1270 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1271 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1272 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ 1273 slew-rate = <0>; 1274 drive-push-pull; 1275 bias-disable; 1276 }; 1277 }; 1278 1279 sai2a_sleep_pins_b: sai2a-sleep-1 { 1280 pins { 1281 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1282 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1283 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ 1284 }; 1285 }; 1286 1287 sai2a_pins_c: sai2a-2 { 1288 pins { 1289 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ 1290 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ 1291 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ 1292 slew-rate = <0>; 1293 drive-push-pull; 1294 bias-disable; 1295 }; 1296 }; 1297 1298 sai2a_sleep_pins_c: sai2a-sleep-2 { 1299 pins { 1300 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ 1301 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ 1302 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ 1303 }; 1304 }; 1305 1306 sai2b_pins_a: sai2b-0 { 1307 pins1 { 1308 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 1309 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 1310 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 1311 slew-rate = <0>; 1312 drive-push-pull; 1313 bias-disable; 1314 }; 1315 pins2 { 1316 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1317 bias-disable; 1318 }; 1319 }; 1320 1321 sai2b_sleep_pins_a: sai2b-sleep-0 { 1322 pins { 1323 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 1324 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 1325 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 1326 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 1327 }; 1328 }; 1329 1330 sai2b_pins_b: sai2b-1 { 1331 pins { 1332 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1333 bias-disable; 1334 }; 1335 }; 1336 1337 sai2b_sleep_pins_b: sai2b-sleep-1 { 1338 pins { 1339 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1340 }; 1341 }; 1342 1343 sai2b_pins_c: sai2b-2 { 1344 pins1 { 1345 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1346 bias-disable; 1347 }; 1348 }; 1349 1350 sai2b_sleep_pins_c: sai2b-sleep-2 { 1351 pins { 1352 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1353 }; 1354 }; 1355 1356 sai4a_pins_a: sai4a-0 { 1357 pins { 1358 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 1359 slew-rate = <0>; 1360 drive-push-pull; 1361 bias-disable; 1362 }; 1363 }; 1364 1365 sai4a_sleep_pins_a: sai4a-sleep-0 { 1366 pins { 1367 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 1368 }; 1369 }; 1370 1371 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 1372 pins1 { 1373 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1374 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1375 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1376 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1377 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1378 slew-rate = <1>; 1379 drive-push-pull; 1380 bias-disable; 1381 }; 1382 pins2 { 1383 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1384 slew-rate = <2>; 1385 drive-push-pull; 1386 bias-disable; 1387 }; 1388 }; 1389 1390 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 1391 pins1 { 1392 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1393 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1394 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1395 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1396 slew-rate = <1>; 1397 drive-push-pull; 1398 bias-disable; 1399 }; 1400 pins2 { 1401 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1402 slew-rate = <2>; 1403 drive-push-pull; 1404 bias-disable; 1405 }; 1406 pins3 { 1407 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1408 slew-rate = <1>; 1409 drive-open-drain; 1410 bias-disable; 1411 }; 1412 }; 1413 1414 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { 1415 pins1 { 1416 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1417 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1418 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1419 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1420 slew-rate = <1>; 1421 drive-push-pull; 1422 bias-disable; 1423 }; 1424 }; 1425 1426 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 1427 pins { 1428 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1429 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1430 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 1431 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1432 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1433 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1434 }; 1435 }; 1436 1437 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 1438 pins1 { 1439 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1440 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1441 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1442 slew-rate = <1>; 1443 drive-push-pull; 1444 bias-pull-up; 1445 }; 1446 pins2{ 1447 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1448 bias-pull-up; 1449 }; 1450 }; 1451 1452 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { 1453 pins1 { 1454 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1455 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1456 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1457 slew-rate = <1>; 1458 drive-push-pull; 1459 bias-pull-up; 1460 }; 1461 }; 1462 1463 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 1464 pins { 1465 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1466 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 1467 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1468 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1469 }; 1470 }; 1471 1472 sdmmc1_dir_pins_b: sdmmc1-dir-1 { 1473 pins1 { 1474 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1475 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ 1476 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1477 slew-rate = <1>; 1478 drive-push-pull; 1479 bias-pull-up; 1480 }; 1481 pins2{ 1482 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1483 bias-pull-up; 1484 }; 1485 }; 1486 1487 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { 1488 pins { 1489 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1490 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ 1491 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1492 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1493 }; 1494 }; 1495 1496 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 1497 pins1 { 1498 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1499 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1500 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1501 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1502 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1503 slew-rate = <1>; 1504 drive-push-pull; 1505 bias-pull-up; 1506 }; 1507 pins2 { 1508 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1509 slew-rate = <2>; 1510 drive-push-pull; 1511 bias-pull-up; 1512 }; 1513 }; 1514 1515 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 1516 pins1 { 1517 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1518 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1519 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1520 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1521 slew-rate = <1>; 1522 drive-push-pull; 1523 bias-pull-up; 1524 }; 1525 pins2 { 1526 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1527 slew-rate = <2>; 1528 drive-push-pull; 1529 bias-pull-up; 1530 }; 1531 pins3 { 1532 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1533 slew-rate = <1>; 1534 drive-open-drain; 1535 bias-pull-up; 1536 }; 1537 }; 1538 1539 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 1540 pins { 1541 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 1542 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 1543 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 1544 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 1545 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 1546 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 1547 }; 1548 }; 1549 1550 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 1551 pins1 { 1552 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1553 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1554 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1555 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1556 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1557 slew-rate = <1>; 1558 drive-push-pull; 1559 bias-disable; 1560 }; 1561 pins2 { 1562 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1563 slew-rate = <2>; 1564 drive-push-pull; 1565 bias-disable; 1566 }; 1567 }; 1568 1569 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 1570 pins1 { 1571 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1572 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1573 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1574 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1575 slew-rate = <1>; 1576 drive-push-pull; 1577 bias-disable; 1578 }; 1579 pins2 { 1580 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1581 slew-rate = <2>; 1582 drive-push-pull; 1583 bias-disable; 1584 }; 1585 pins3 { 1586 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1587 slew-rate = <1>; 1588 drive-open-drain; 1589 bias-disable; 1590 }; 1591 }; 1592 1593 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 1594 pins { 1595 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1596 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1597 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1598 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1599 slew-rate = <1>; 1600 drive-push-pull; 1601 bias-pull-up; 1602 }; 1603 }; 1604 1605 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 1606 pins { 1607 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1608 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1609 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1610 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1611 }; 1612 }; 1613 1614 sdmmc2_d47_pins_b: sdmmc2-d47-1 { 1615 pins { 1616 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1617 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1618 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1619 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1620 slew-rate = <1>; 1621 drive-push-pull; 1622 bias-disable; 1623 }; 1624 }; 1625 1626 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { 1627 pins { 1628 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1629 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1630 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1631 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1632 }; 1633 }; 1634 1635 sdmmc2_d47_pins_c: sdmmc2-d47-2 { 1636 pins { 1637 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1638 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ 1639 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1640 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1641 slew-rate = <1>; 1642 drive-push-pull; 1643 bias-pull-up; 1644 }; 1645 }; 1646 1647 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { 1648 pins { 1649 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1650 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ 1651 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1652 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1653 }; 1654 }; 1655 1656 sdmmc2_d47_pins_d: sdmmc2-d47-3 { 1657 pins { 1658 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1659 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1660 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1661 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1662 }; 1663 }; 1664 1665 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { 1666 pins { 1667 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1668 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1669 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1670 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1671 }; 1672 }; 1673 1674 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 1675 pins1 { 1676 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1677 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1678 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1679 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1680 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 1681 slew-rate = <1>; 1682 drive-push-pull; 1683 bias-pull-up; 1684 }; 1685 pins2 { 1686 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1687 slew-rate = <2>; 1688 drive-push-pull; 1689 bias-pull-up; 1690 }; 1691 }; 1692 1693 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 1694 pins1 { 1695 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1696 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1697 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1698 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1699 slew-rate = <1>; 1700 drive-push-pull; 1701 bias-pull-up; 1702 }; 1703 pins2 { 1704 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1705 slew-rate = <2>; 1706 drive-push-pull; 1707 bias-pull-up; 1708 }; 1709 pins3 { 1710 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 1711 slew-rate = <1>; 1712 drive-open-drain; 1713 bias-pull-up; 1714 }; 1715 }; 1716 1717 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 1718 pins { 1719 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1720 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1721 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 1722 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1723 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1724 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 1725 }; 1726 }; 1727 1728 sdmmc3_b4_pins_b: sdmmc3-b4-1 { 1729 pins1 { 1730 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1731 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1732 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1733 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1734 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 1735 slew-rate = <1>; 1736 drive-push-pull; 1737 bias-pull-up; 1738 }; 1739 pins2 { 1740 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1741 slew-rate = <2>; 1742 drive-push-pull; 1743 bias-pull-up; 1744 }; 1745 }; 1746 1747 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { 1748 pins1 { 1749 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1750 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1751 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1752 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1753 slew-rate = <1>; 1754 drive-push-pull; 1755 bias-pull-up; 1756 }; 1757 pins2 { 1758 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1759 slew-rate = <2>; 1760 drive-push-pull; 1761 bias-pull-up; 1762 }; 1763 pins3 { 1764 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ 1765 slew-rate = <1>; 1766 drive-open-drain; 1767 bias-pull-up; 1768 }; 1769 }; 1770 1771 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { 1772 pins { 1773 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1774 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1775 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 1776 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1777 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1778 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 1779 }; 1780 }; 1781 1782 spdifrx_pins_a: spdifrx-0 { 1783 pins { 1784 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 1785 bias-disable; 1786 }; 1787 }; 1788 1789 spdifrx_sleep_pins_a: spdifrx-sleep-0 { 1790 pins { 1791 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 1792 }; 1793 }; 1794 1795 spi2_pins_a: spi2-0 { 1796 pins1 { 1797 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ 1798 <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ 1799 bias-disable; 1800 drive-push-pull; 1801 slew-rate = <1>; 1802 }; 1803 1804 pins2 { 1805 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ 1806 bias-disable; 1807 }; 1808 }; 1809 1810 spi4_pins_a: spi4-0 { 1811 pins { 1812 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ 1813 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ 1814 bias-disable; 1815 drive-push-pull; 1816 slew-rate = <1>; 1817 }; 1818 pins2 { 1819 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ 1820 bias-disable; 1821 }; 1822 }; 1823 1824 stusb1600_pins_a: stusb1600-0 { 1825 pins { 1826 pinmux = <STM32_PINMUX('I', 11, GPIO)>; 1827 bias-pull-up; 1828 }; 1829 }; 1830 1831 uart4_pins_a: uart4-0 { 1832 pins1 { 1833 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1834 bias-disable; 1835 drive-push-pull; 1836 slew-rate = <0>; 1837 }; 1838 pins2 { 1839 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1840 bias-disable; 1841 }; 1842 }; 1843 1844 uart4_idle_pins_a: uart4-idle-0 { 1845 pins1 { 1846 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ 1847 }; 1848 pins2 { 1849 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1850 bias-disable; 1851 }; 1852 }; 1853 1854 uart4_sleep_pins_a: uart4-sleep-0 { 1855 pins { 1856 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ 1857 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 1858 }; 1859 }; 1860 1861 uart4_pins_b: uart4-1 { 1862 pins1 { 1863 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 1864 bias-disable; 1865 drive-push-pull; 1866 slew-rate = <0>; 1867 }; 1868 pins2 { 1869 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1870 bias-disable; 1871 }; 1872 }; 1873 1874 uart4_pins_c: uart4-2 { 1875 pins1 { 1876 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1877 bias-disable; 1878 drive-push-pull; 1879 slew-rate = <0>; 1880 }; 1881 pins2 { 1882 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1883 bias-disable; 1884 }; 1885 }; 1886 1887 uart7_pins_a: uart7-0 { 1888 pins1 { 1889 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 1890 bias-disable; 1891 drive-push-pull; 1892 slew-rate = <0>; 1893 }; 1894 pins2 { 1895 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ 1896 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ 1897 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ 1898 bias-disable; 1899 }; 1900 }; 1901 1902 uart7_pins_b: uart7-1 { 1903 pins1 { 1904 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ 1905 bias-disable; 1906 drive-push-pull; 1907 slew-rate = <0>; 1908 }; 1909 pins2 { 1910 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ 1911 bias-disable; 1912 }; 1913 }; 1914 1915 uart7_pins_c: uart7-2 { 1916 pins1 { 1917 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 1918 bias-disable; 1919 drive-push-pull; 1920 slew-rate = <0>; 1921 }; 1922 pins2 { 1923 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 1924 bias-pull-up; 1925 }; 1926 }; 1927 1928 uart7_idle_pins_c: uart7-idle-2 { 1929 pins1 { 1930 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ 1931 }; 1932 pins2 { 1933 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 1934 bias-pull-up; 1935 }; 1936 }; 1937 1938 uart7_sleep_pins_c: uart7-sleep-2 { 1939 pins { 1940 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ 1941 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ 1942 }; 1943 }; 1944 1945 uart8_pins_a: uart8-0 { 1946 pins1 { 1947 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 1948 bias-disable; 1949 drive-push-pull; 1950 slew-rate = <0>; 1951 }; 1952 pins2 { 1953 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ 1954 bias-disable; 1955 }; 1956 }; 1957 1958 uart8_rtscts_pins_a: uart8rtscts-0 { 1959 pins { 1960 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ 1961 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ 1962 bias-disable; 1963 }; 1964 }; 1965 1966 usart2_pins_a: usart2-0 { 1967 pins1 { 1968 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 1969 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 1970 bias-disable; 1971 drive-push-pull; 1972 slew-rate = <0>; 1973 }; 1974 pins2 { 1975 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 1976 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 1977 bias-disable; 1978 }; 1979 }; 1980 1981 usart2_sleep_pins_a: usart2-sleep-0 { 1982 pins { 1983 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 1984 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1985 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 1986 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 1987 }; 1988 }; 1989 1990 usart2_pins_b: usart2-1 { 1991 pins1 { 1992 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 1993 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1994 bias-disable; 1995 drive-push-pull; 1996 slew-rate = <0>; 1997 }; 1998 pins2 { 1999 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ 2000 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ 2001 bias-disable; 2002 }; 2003 }; 2004 2005 usart2_sleep_pins_b: usart2-sleep-1 { 2006 pins { 2007 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2008 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 2009 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ 2010 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 2011 }; 2012 }; 2013 2014 usart2_pins_c: usart2-2 { 2015 pins1 { 2016 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 2017 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2018 bias-disable; 2019 drive-push-pull; 2020 slew-rate = <3>; 2021 }; 2022 pins2 { 2023 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2024 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2025 bias-disable; 2026 }; 2027 }; 2028 2029 usart2_idle_pins_c: usart2-idle-2 { 2030 pins1 { 2031 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2032 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2033 }; 2034 pins2 { 2035 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2036 bias-disable; 2037 drive-push-pull; 2038 slew-rate = <3>; 2039 }; 2040 pins3 { 2041 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 2042 bias-disable; 2043 }; 2044 }; 2045 2046 usart2_sleep_pins_c: usart2-sleep-2 { 2047 pins { 2048 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2049 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2050 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2051 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2052 }; 2053 }; 2054 2055 usart3_pins_a: usart3-0 { 2056 pins1 { 2057 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 2058 bias-disable; 2059 drive-push-pull; 2060 slew-rate = <0>; 2061 }; 2062 pins2 { 2063 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2064 bias-disable; 2065 }; 2066 }; 2067 2068 usart3_pins_b: usart3-1 { 2069 pins1 { 2070 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2071 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2072 bias-disable; 2073 drive-push-pull; 2074 slew-rate = <0>; 2075 }; 2076 pins2 { 2077 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2078 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 2079 bias-pull-up; 2080 }; 2081 }; 2082 2083 usart3_idle_pins_b: usart3-idle-1 { 2084 pins1 { 2085 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2086 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ 2087 }; 2088 pins2 { 2089 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2090 bias-disable; 2091 drive-push-pull; 2092 slew-rate = <0>; 2093 }; 2094 pins3 { 2095 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2096 bias-pull-up; 2097 }; 2098 }; 2099 2100 usart3_sleep_pins_b: usart3-sleep-1 { 2101 pins { 2102 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2103 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2104 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ 2105 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2106 }; 2107 }; 2108 2109 usart3_pins_c: usart3-2 { 2110 pins1 { 2111 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2112 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2113 bias-disable; 2114 drive-push-pull; 2115 slew-rate = <0>; 2116 }; 2117 pins2 { 2118 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2119 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 2120 bias-pull-up; 2121 }; 2122 }; 2123 2124 usart3_idle_pins_c: usart3-idle-2 { 2125 pins1 { 2126 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2127 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ 2128 }; 2129 pins2 { 2130 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2131 bias-disable; 2132 drive-push-pull; 2133 slew-rate = <0>; 2134 }; 2135 pins3 { 2136 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2137 bias-pull-up; 2138 }; 2139 }; 2140 2141 usart3_sleep_pins_c: usart3-sleep-2 { 2142 pins { 2143 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2144 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2145 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ 2146 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2147 }; 2148 }; 2149 2150 usart3_pins_d: usart3-3 { 2151 pins1 { 2152 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2153 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2154 bias-disable; 2155 drive-push-pull; 2156 slew-rate = <0>; 2157 }; 2158 pins2 { 2159 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ 2160 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2161 bias-disable; 2162 }; 2163 }; 2164 2165 usart3_idle_pins_d: usart3-idle-3 { 2166 pins1 { 2167 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2168 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2169 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2170 }; 2171 pins2 { 2172 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ 2173 bias-disable; 2174 }; 2175 }; 2176 2177 usart3_sleep_pins_d: usart3-sleep-3 { 2178 pins { 2179 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2180 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2181 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2182 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ 2183 }; 2184 }; 2185 2186 usbotg_hs_pins_a: usbotg-hs-0 { 2187 pins { 2188 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 2189 }; 2190 }; 2191 2192 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 2193 pins { 2194 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 2195 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 2196 }; 2197 }; 2198}; 2199 2200&pinctrl_z { 2201 i2c2_pins_b2: i2c2-0 { 2202 pins { 2203 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 2204 bias-disable; 2205 drive-open-drain; 2206 slew-rate = <0>; 2207 }; 2208 }; 2209 2210 i2c2_sleep_pins_b2: i2c2-sleep-0 { 2211 pins { 2212 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 2213 }; 2214 }; 2215 2216 i2c4_pins_a: i2c4-0 { 2217 pins { 2218 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 2219 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 2220 bias-disable; 2221 drive-open-drain; 2222 slew-rate = <0>; 2223 }; 2224 }; 2225 2226 i2c4_sleep_pins_a: i2c4-sleep-0 { 2227 pins { 2228 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 2229 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 2230 }; 2231 }; 2232 2233 i2c6_pins_a: i2c6-0 { 2234 pins { 2235 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ 2236 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ 2237 bias-disable; 2238 drive-open-drain; 2239 slew-rate = <0>; 2240 }; 2241 }; 2242 2243 i2c6_sleep_pins_a: i2c6-sleep-0 { 2244 pins { 2245 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ 2246 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ 2247 }; 2248 }; 2249 2250 spi1_pins_a: spi1-0 { 2251 pins1 { 2252 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 2253 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 2254 bias-disable; 2255 drive-push-pull; 2256 slew-rate = <1>; 2257 }; 2258 2259 pins2 { 2260 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 2261 bias-disable; 2262 }; 2263 }; 2264 2265 spi1_pins_b: spi1-1 { 2266 pins1 { 2267 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ 2268 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ 2269 bias-disable; 2270 drive-push-pull; 2271 slew-rate = <1>; 2272 }; 2273 2274 pins2 { 2275 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ 2276 bias-disable; 2277 }; 2278 }; 2279}; 2280