1# Format of file 2# <reg-name> <CRn> <opc1> <CRm> <opc2> <Type> <Description> 3# lines beginning with '@' will be printed as additional comments 4 5@ Based on register description in 6@ ARM Generic Interrupt Controller 7@ Architecture Specification 8@ GIC architecture version 3.0 and version 4.0 9 10@ Table 8-7 Mapping of MCR and MRC to physical and virtual CPU interface registers, AArch32 state 11ICC_AP0R0 c12 0 c8 4 RW 12ICC_AP0R1 c12 0 c8 5 RW 13ICC_AP0R2 c12 0 c8 6 RW 14ICC_AP0R3 c12 0 c8 7 RW 15ICC_AP1R0 c12 0 c9 0 RW 16ICC_AP1R1 c12 0 c9 1 RW 17ICC_AP1R2 c12 0 c9 2 RW 18ICC_AP1R3 c12 0 c9 3 RW 19ICC_ASGI1R - 1 c12 - WO 20ICC_BPR0 c12 0 c8 3 RW 21ICC_BPR1 c12 0 c12 3 RW 22ICC_CTLR c12 0 c12 4 RW 23ICC_DIR c12 0 c11 1 WO 24ICC_EOIR0 c12 0 c8 1 WO 25ICC_EOIR1 c12 0 c12 1 WO 26ICC_HPPIR0 c12 0 c8 2 RO 27ICC_HPPIR1 c12 0 c12 2 RO 28ICC_HSRE c12 4 c9 5 RW 29ICC_IAR0 c12 0 c8 0 RO 30ICC_IAR1 c12 0 c12 0 RO 31ICC_IGRPEN0 c12 0 c12 6 RW 32ICC_IGRPEN1 c12 0 c12 7 RW 33ICC_MCTLR c12 6 c12 4 RW 34ICC_MGRPEN1 c12 6 c12 7 RW 35ICC_MSRE c12 6 c12 5 RW 36ICC_PMR c4 0 c6 0 RW 37ICC_RPR c12 0 c11 3 RO 38ICC_SGI0R - 2 c12 - WO 39ICC_SGI1R - 0 c12 - WO 40ICC_SRE c12 0 c12 5 RW 41