1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 64 13 14 /* UART */ 15 #define PERI_SUB_CTRL_ADDR 0x80000000 16 #define CONSOLE_UART_BASE (PERI_SUB_CTRL_ADDR + 0x00300000) 17 #define CONSOLE_BAUDRATE 115200 18 #define CONSOLE_UART_CLK_IN_HZ 200000000 19 20 /* ALG sub-controller */ 21 #define ALG_SC_BASE 0xD0000000 22 #define ALG_SC_REG_SIZE 0xF010 23 24 /* RNG */ 25 #define RNG_BASE 0xD1010000 26 #define RNG_REG_SIZE 0x18 27 28 /* 29 * HiSilicon D02 memory map 30 * 31 * Note: the physical address ranges below correspond to DRAM which is 32 * non-secure by default. Therefore, the terms TZDRAM and TZSRAM may not 33 * reflect the reality and only indicate areas that "would normally be" 34 * secure DRAM and secure SRAM in a more complete implementation. 35 * The memory map was defined like this for lack of better documentation. 36 * It is good enough for development/testing purposes. 37 * 38 * CFG_WITH_PAGER=n 39 * 40 * 0x7FC0_0000 - 41 * Linux/other | DRAM1 42 * 0x5180_0000 - 43 * TA RAM: 16 MiB | 44 * 0x5080_0000 | TZDRAM 45 * TEE RAM: 4 MiB (TEE_RAM_VA_SIZE) | 46 * 0x5040_0000 [TZDRAM_BASE, TEE_LOAD_ADDR] - 47 * Shared memory: 4 MiB | SHMEM 48 * 0x5000_0000 - 49 * Linux/other | DRAM0 50 * 0x0000_0000 [DRAM0_BASE] - 51 * 52 * CFG_WITH_PAGER=y 53 * 54 * 0x7FC0_0000 - 55 * Linux/other | DRAM1 56 * 0x5180_0000 - 57 * TA RAM: 20096 KiB (TZDRAM_SIZE) | TZDRAM 58 * 0x5046_0000 - 59 * TEE RAM: 384 KiB (TZSRAM_SIZE) | TZSRAM 60 * 0x5040_0000 [TZSRAM_BASE, TEE_LOAD_ADDR] - 61 * Shared memory: 4 MiB | SHMEM 62 * 0x5000_0000 - 63 * Linux/other | DRAM0 64 * 0x0000_0000 [DRAM0_BASE] - 65 */ 66 67 #define DRAM0_BASE 0x00000000 68 #define DRAM0_SIZE 0x50000000 69 70 #define DRAM1_BASE 0x51800000 71 #define DRAM1_SIZE 0x2E400000 72 73 #endif /* PLATFORM_CONFIG_H */ 74