1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 64 13 14 /* PL011 UART */ 15 #if defined(PLATFORM_FLAVOR_hikey) 16 17 #define PL011_UART0_BASE 0xF8015000 18 #define PL011_UART2_BASE 0xF7112000 19 #define PL011_UART3_BASE 0xF7113000 20 #if (CFG_CONSOLE_UART == 3) 21 #define CONSOLE_UART_BASE PL011_UART3_BASE 22 #elif (CFG_CONSOLE_UART == 2) 23 #define CONSOLE_UART_BASE PL011_UART2_BASE 24 #elif (CFG_CONSOLE_UART == 0) 25 #define CONSOLE_UART_BASE PL011_UART0_BASE 26 #else 27 #error Unknown console UART 28 #endif 29 30 #elif defined(PLATFORM_FLAVOR_hikey960) 31 32 #define PL011_UART5_BASE 0xFDF05000 33 #define PL011_UART6_BASE 0xFFF32000 34 #if (CFG_CONSOLE_UART == 6) 35 #define CONSOLE_UART_BASE PL011_UART6_BASE 36 #elif (CFG_CONSOLE_UART == 5) 37 #define CONSOLE_UART_BASE PL011_UART5_BASE 38 #else 39 #error Unknown console UART 40 #endif 41 42 #else /* PLATFORM_FLAVOR_hikey */ 43 #error Unknown HiKey PLATFORM_FLAVOR 44 #endif /* PLATFORM_FLAVOR_hikey */ 45 46 #define CONSOLE_BAUDRATE 115200 47 #define CONSOLE_UART_CLK_IN_HZ 19200000 48 49 /* 50 * HiKey and HiKey960 memory map 51 * 52 * Refer to the default configuration from conf.mk for description below. 53 * 54 * TZDRAM is secured (firewalled) by the DDR controller, see ARM-TF, but note 55 * that security of this type of memory is weak for two reasons: 56 * 1. It is prone to physical tampering since DRAM is external to the SoC 57 * 2. It is still somewhat prone to software attacks because the memory 58 * protection may be reverted by the non-secure kernel with a piece of 59 * code similar to the one that sets the protection in ARM-TF (we're 60 * missing a "lockdown" step which would prevent any change to the DDRC 61 * configuration until the next SoC reset). 62 * TZSRAM is emulated in the TZDRAM area, because the on-chip SRAM of the 63 * HiKey SoC is too small to run OP-TEE (72K total with 64K available, see 64 * "SRAM Memory Region Layout" in ARM-TF plat/hikey/include/hisi_sram_map.h), 65 * while the SRAM of the HiKey960 SoC is not available to the public at the 66 * moment. 67 * 68 * CFG_WITH_PAGER=n 69 * 70 * 0x4000_0000 - 71 * TA RAM: 14 MiB | 72 * 0x3F20_0000 | TZDRAM 73 * TEE RAM: 2 MiB (TEE_RAM_VA_SIZE) | 74 * 0x3F00_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] - 75 * Shared memory: 2 MiB | 76 * 0x3EE0_0000 | DRAM0 77 * Reserved by UEFI for OP-TEE, unused | 78 * 0x3EC0_0000 - 79 * Secure Data Path buffers: 4 MiB | DRAM0 (secure) 80 * 0x3E80_0000 [CFG_TEE_SDP_MEM_BASE] - 81 * Reserved by UEFI for OP-TEE, unused | 82 * 0x3E00_0000 | DRAM0 83 * Available to Linux | 84 * 0x0000_0000 [DRAM0_BASE] - 85 * 86 * CFG_WITH_PAGER=y 87 * 88 * 0x4000_0000 - 89 * TA RAM: 14 MiB | TZDRAM 90 * 0x3F20_0000 - 91 * Unused 92 * 0x3F03_2000 - 93 * TEE RAM: 200 KiB | TZSRAM 94 * 0x3F00_0000 [TZSRAM_BASE, BL32_LOAD_ADDR] - 95 * Shared memory: 2 MiB | 96 * 0x3EE0_0000 | DRAM0 97 * Reserved by UEFI for OP-TEE, unused | 98 * 0x3EC0_0000 - 99 * Secure Data Path buffers: 4 MiB | DRAM0 (secure) 100 * 0x3E80_0000 [CFG_TEE_SDP_MEM_BASE] - 101 * Reserved by UEFI for OP-TEE, unused | 102 * 0x3E00_0000 | DRAM0 103 * Available to Linux | 104 * 0x0000_0000 [DRAM0_BASE] - 105 */ 106 107 #define DRAM0_BASE 0x00000000 108 #define DRAM0_SIZE 0x3F000000 109 #define DRAM0_SIZE_NSEC 0x3E000000 110 #define DRAM1_BASE 0x40000000 111 112 #if defined(PLATFORM_FLAVOR_hikey) 113 114 #if (CFG_DRAM_SIZE_GB == 2) 115 #define DRAM1_SIZE_NSEC 0x40000000 116 #elif (CFG_DRAM_SIZE_GB == 1) 117 /* do nothing */ 118 #else 119 #error Unknown DRAM size 120 #endif 121 122 #elif defined(PLATFORM_FLAVOR_hikey960) 123 124 /* 125 * Physical address ranges for HiKey960 RAM: 126 * 3G board: 0~3G 127 * 4G board: 0~3G 3~3.5G 8~8.5G 128 * 6G board: 0~3G 4~7G 129 */ 130 #if (CFG_DRAM_SIZE_GB == 3) 131 #define DRAM1_SIZE_NSEC 0x80000000 132 #elif (CFG_DRAM_SIZE_GB == 4) 133 #define DRAM1_SIZE_NSEC 0xA0000000 134 #define DRAM2_BASE 0x200000000 135 #define DRAM2_SIZE_NSEC 0x20000000 136 #elif (CFG_DRAM_SIZE_GB == 6) 137 #define DRAM1_SIZE_NSEC 0x80000000 138 #define DRAM2_BASE 0x100000000 139 #define DRAM2_SIZE_NSEC 0xC0000000 140 #else 141 #error Unknown DRAM size 142 #endif 143 144 #if (CFG_DRAM_SIZE_GB >= 4 && defined(CFG_ARM32_core) && \ 145 defined(CFG_CORE_DYN_SHM) && !defined(CFG_LARGE_PHYS_ADDR)) 146 #error 32-bit TEE with CFG_CORE_DYN_SHM and without CFG_LARGE_PHYS_ADDR \ 147 cannot support boards with 4G RAM or more 148 #endif 149 150 #else /* PLATFORM_FLAVOR_hikey */ 151 #error Unknown HiKey PLATFORM_FLAVOR 152 #endif /* PLATFORM_FLAVOR_hikey */ 153 154 #endif /* PLATFORM_CONFIG_H */ 155