1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright 2017-2019 NXP
4 *
5 * Peng Fan  <peng.fan@nxp.com>
6 */
7
8/*
9 * Entry points for the A7 init.
10 * It is assume no stack is available when these routines are called.
11 * It is assume each routine is called with return address in LR
12 * and with ARM registers R0, R1, R2, R3 being scratchable.
13 */
14
15#include <arm.h>
16#include <arm32.h>
17#include <arm32_macros.S>
18#include <asm.S>
19#include <platform_config.h>
20
21.section .text
22.balign 4
23.code 32
24
25/*
26 * Cortex A7 configuration early configuration
27 *
28 * Use scratables registers R0-R3.
29 * No stack usage.
30 * LR store return address.
31 * Trap CPU in case of error.
32 */
33FUNC plat_cpu_reset_early , :
34	/*
35	 * DDI: Disable dual issue [bit28=0]
36	 * DDVM: Disable Distributed Virtual Memory transactions [bit15=0]
37	 * L1PCTL: L1 Data prefetch control [bit14:13=2b11]
38	 * L1RADIS: L1 Data Cache read-allocate mode disable [bit12=0]
39	 * L2RADIS: L2 Data Cache read-allocate mode disable [bit11=0]
40	 * DODMBS: Disable optimized data memory barrier behavior [bit10=0]
41	 * SMP: Enables coherent requests to the processor [bit6=0]
42	 */
43	mov_imm r0, 0x00006040
44	write_actlr r0
45
46	mov_imm r0, 0x00040C00
47	write_nsacr r0
48
49	bx	lr
50END_FUNC plat_cpu_reset_early
51
52FUNC get_core_pos_mpidr , :
53	/* Drop ClusterId. There is no SoCs with more than 4 A7 Cores. */
54	and	r0, r0, #MPIDR_CPU_MASK
55	bx	lr
56END_FUNC get_core_pos_mpidr
57