1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2017-2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef CONFIG_IMX6QDLSOLO_H 32 #define CONFIG_IMX6QDLSOLO_H 33 34 /* 35 * PL310 TAG RAM Control Register 36 * 37 * bit[10:8]:1 - 2 cycle of write accesses latency 38 * bit[6:4]:3 - 4 cycle of read accesses latency 39 * bit[2:0]:2 - 3 cycle of setup latency 40 */ 41 #ifndef PL310_TAG_RAM_CTRL_INIT 42 #define PL310_TAG_RAM_CTRL_INIT 0x00000132 43 #endif 44 45 /* 46 * PL310 DATA RAM Control Register 47 * 48 * bit[10:8]:1 - 2 cycle of write accesses latency 49 * bit[6:4]:3 - 4 cycle of read accesses latency 50 * bit[2:0]:2 - 3 cycle of setup latency 51 */ 52 #ifndef PL310_DATA_RAM_CTRL_INIT 53 #define PL310_DATA_RAM_CTRL_INIT 0x00000132 54 #endif 55 56 /* 57 * PL310 Auxiliary Control Register 58 */ 59 #ifndef PL310_AUX_CTRL_INIT 60 #if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) 61 /* 62 * Early BRESP enabled (bit30=1) 63 * I/Dcache prefetch enabled (bit29:28=2b11) 64 * NS can access interrupts (bit27=1) 65 * NS can lockown cache lines (bit26=1) 66 * Pseudo-random replacement policy (bit25=1) 67 * Force write allocated (default) (bit24:23=00) 68 * Shared attribute internally ignored (bit22=1, bit13=0) 69 * Parity disabled (bit21=0) 70 * Event monitor disabled (bit20=0) 71 * 64kb way size (bit19:17=3b011) 72 * 16-way associativity (bit16=1) 73 * Store buffer device limitation disabled (bit11=0) 74 * Cacheable accesses have high prio (bit10=0) 75 * Full Line Zero (FLZ) enabled (bit0=1) 76 */ 77 #define PL310_AUX_CTRL_INIT 0x7E470001 78 #else 79 /* 80 * Early BRESP enabled (bit30=0) 81 * I/Dcache prefetch enabled (bit29:28=2b11) 82 * NS can access interrupts (bit27=1) 83 * NS can lockown cache lines (bit26=1) 84 * Pseudo-random replacement policy (bit25=0) 85 * Force write allocated (default) (bit24:23=00) 86 * Shared attribute internally ignored (bit22=1, bit13=0) 87 * Parity disabled (bit21=0) 88 * Event monitor disabled (bit20=0) 89 * 32kb way size (bit19:17=3b010) 90 * 8-way associativity (bit16=0) 91 * Store buffer device limitation enabled (bit11=1) 92 * Cacheable accesses have high prio (bit10=0) 93 * Full Line Zero (FLZ) disabled (bit0=0) 94 */ 95 #define PL310_AUX_CTRL_INIT 0x3C440800 96 #endif 97 #endif 98 99 /* 100 * PL310 Prefetch Control Register 101 * 102 * Double linefill enabled (bit30=1) 103 * I/D prefetch enabled (bit29:28=2b11) 104 * Prefetch drop disabled (bit24=0) 105 * Incr double linefill disable (bit23=0) 106 * Prefetch offset = 0xF (bit4:0) 107 */ 108 #define PL310_PREFETCH_CTRL_INIT 0x7000000F 109 110 /* 111 * PL310 Power Register 112 * 113 * Dynamic clock gating enabled 114 * Standby mode enabled 115 */ 116 #define PL310_POWER_CTRL_INIT 0x00000003 117 118 /* 119 * SCU Invalidate Register 120 * 121 * Invalidate all registers 122 */ 123 #define SCU_INV_CTRL_INIT 0xFFFFFFFF 124 125 /* 126 * SCU Access Register 127 * - both secure CPU access SCU 128 */ 129 #define SCU_SAC_CTRL_INIT 0x0000000F 130 131 /* 132 * SCU NonSecure Access Register 133 * - both nonsec cpu access SCU, private and global timer 134 */ 135 #define SCU_NSAC_CTRL_INIT 0x00000FFF 136 137 #endif 138