1PLATFORM_FLAVOR ?= ls1012ardb 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 12include core/arch/arm/cpu/cortex-armv8-0.mk 13$(call force,CFG_TEE_CORE_NB_CORE,1) 14$(call force,CFG_DRAM0_SIZE,0x40000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_NUM_THREADS ?= 2 17CFG_SHMEM_SIZE ?= 0x00200000 18endif 19 20ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 21include core/arch/arm/cpu/cortex-armv8-0.mk 22$(call force,CFG_TEE_CORE_NB_CORE,4) 23$(call force,CFG_DRAM0_SIZE,0x80000000) 24$(call force,CFG_CORE_CLUSTER_SHIFT,2) 25CFG_SHMEM_SIZE ?= 0x00200000 26endif 27 28ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 29include core/arch/arm/cpu/cortex-armv8-0.mk 30$(call force,CFG_TEE_CORE_NB_CORE,4) 31$(call force,CFG_DRAM0_SIZE,0x80000000) 32$(call force,CFG_CORE_CLUSTER_SHIFT,2) 33CFG_SHMEM_SIZE ?= 0x00200000 34endif 35 36ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 37include core/arch/arm/cpu/cortex-armv8-0.mk 38$(call force,CFG_TEE_CORE_NB_CORE,8) 39$(call force,CFG_DRAM0_SIZE,0x80000000) 40$(call force,CFG_CORE_CLUSTER_SHIFT,2) 41$(call force,CFG_ARM_GICV3,y) 42CFG_SHMEM_SIZE ?= 0x00200000 43endif 44 45ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 46include core/arch/arm/cpu/cortex-armv8-0.mk 47$(call force,CFG_TEE_CORE_NB_CORE,8) 48$(call force,CFG_DRAM0_SIZE,0x80000000) 49$(call force,CFG_CORE_CLUSTER_SHIFT,1) 50$(call force,CFG_ARM_GICV3,y) 51CFG_SHMEM_SIZE ?= 0x00200000 52endif 53 54ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 55include core/arch/arm/cpu/cortex-armv8-0.mk 56$(call force,CFG_TEE_CORE_NB_CORE,16) 57$(call force,CFG_DRAM0_SIZE,0x80000000) 58$(call force,CFG_DRAM1_BASE,0x2080000000) 59$(call force,CFG_DRAM1_SIZE,0x1F80000000) 60$(call force,CFG_CORE_CLUSTER_SHIFT,1) 61$(call force,CFG_ARM_GICV3,y) 62$(call force,CFG_PL011,y) 63$(call force,CFG_CORE_ARM64_PA_BITS,48) 64$(call force,CFG_EMBED_DTB,y) 65$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 66CFG_LS_I2C ?= y 67CFG_LS_GPIO ?= y 68CFG_LS_DSPI ?= y 69CFG_SHMEM_SIZE ?= 0x00200000 70endif 71 72ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 73include core/arch/arm/cpu/cortex-armv8-0.mk 74$(call force,CFG_TEE_CORE_NB_CORE,16) 75$(call force,CFG_DRAM0_SIZE,0x80000000) 76$(call force,CFG_DRAM1_BASE,0x2080000000) 77$(call force,CFG_DRAM1_SIZE,0x1F80000000) 78$(call force,CFG_CORE_CLUSTER_SHIFT,1) 79$(call force,CFG_ARM_GICV3,y) 80$(call force,CFG_PL011,y) 81$(call force,CFG_CORE_ARM64_PA_BITS,48) 82$(call force,CFG_EMBED_DTB,y) 83$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 84CFG_LS_I2C ?= y 85CFG_LS_GPIO ?= y 86CFG_LS_DSPI ?= y 87CFG_SHMEM_SIZE ?= 0x00200000 88endif 89 90ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 91include core/arch/arm/cpu/cortex-armv8-0.mk 92$(call force,CFG_TEE_CORE_NB_CORE,2) 93$(call force,CFG_DRAM0_SIZE,0x80000000) 94$(call force,CFG_CORE_CLUSTER_SHIFT,1) 95$(call force,CFG_ARM_GICV3,y) 96CFG_SHMEM_SIZE ?= 0x00200000 97endif 98 99ifeq ($(platform-flavor-armv8),1) 100$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 101CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 102CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 103#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 104CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 105$(call force,CFG_ARM64_core,y) 106CFG_USER_TA_TARGETS ?= ta_arm64 107else 108#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 109CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 110CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 111#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 112CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 113endif 114 115#Keeping Number of TEE thread equal to number of cores on the SoC 116CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 117 118ifneq ($(CFG_ARM64_core),y) 119$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 120endif 121 122CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 123 124# NXP CAAM support is not enabled by default and can be enabled 125# on the command line 126CFG_NXP_CAAM ?= n 127 128ifneq ($(CFG_NXP_CAAM),y) 129$(call force,CFG_WITH_SOFTWARE_PRNG,y) 130endif 131