1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2017 Marvell International Ltd. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 #include <util.h> 34 35 /* Make stacks aligned to data cache line length */ 36 #define STACK_ALIGNMENT 64 37 38 #ifdef ARM64 39 #ifdef CFG_WITH_PAGER 40 #error "Pager not supported yet" 41 #endif 42 #else 43 #error "32 bit mode not supported yet" 44 #endif /*ARM64*/ 45 46 #if defined(PLATFORM_FLAVOR_armada7k8k) 47 /* 48 * armada7k8k specifics. 49 */ 50 #define TEE_RES_CFG_8M 51 52 #define MVEBU_REGS_BASE 0xF0000000 53 54 /* GICv2 */ 55 #define MVEBU_GICD_BASE 0x210000 56 #define MVEBU_GICC_BASE 0x220000 57 #define GIC_DIST_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) 58 #define GIC_CPU_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) 59 60 #define GIC_BASE GIC_DIST_BASE 61 62 /* UART */ 63 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000) 64 #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 200000000 65 #define MARVELL_CONSOLE_BAUDRATE 115200 66 67 #define CONSOLE_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 68 69 #define GICC_OFFSET 0x10000 70 #define GICD_OFFSET 0x0 71 72 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 73 #define GICC_BASE (GIC_BASE + GICC_OFFSET) 74 75 /* MCU */ 76 #define MCU_BASE 0xF0020000 77 #define MCU_REG_SIZE SIZE_4K 78 #define MC_SCR_REGISTER 0xF06F0204 79 #define MC_SCR_REG_SIZE SIZE_4K 80 81 #elif defined(PLATFORM_FLAVOR_armada3700) 82 /* 83 * armada3700 specifics. 84 */ 85 #define TEE_RES_CFG_8M 86 87 #define MVEBU_REGS_BASE 0xD0000000 88 89 /* GICv3 */ 90 #define MVEBU_GICD_BASE 0x1D00000 91 #define MVEBU_GICR_BASE 0x1D40000 92 #define MVEBU_GICC_BASE 0x1D80000 93 94 #define GIC_DIST_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) 95 #define GIC_RDIS_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) 96 #define GIC_CPU_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) 97 98 #define GIC_BASE GIC_DIST_BASE 99 #define GICC_OFFSET (0x80000) 100 #define GICR_OFFSET (0x40000) 101 #define GICD_OFFSET (0x0) 102 103 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 104 #define GICC_BASE (GIC_BASE + GICC_OFFSET) 105 106 /* UART */ 107 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000) 108 #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800 109 #define MARVELL_CONSOLE_BAUDRATE 115200 110 #define CONSOLE_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 111 112 #elif defined(PLATFORM_FLAVOR_otx2t96) || defined(PLATFORM_FLAVOR_otx2f95) || \ 113 defined(PLATFORM_FLAVOR_otx2t98) 114 /* 115 * OcteonTX2(otx2) specifics. 116 */ 117 118 /* GICv3 */ 119 #define GIC_BASE 0x801000000000ll 120 #define GICD_OFFSET (0x0) 121 122 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 123 124 /* UART */ 125 #define PLAT_MARVELL_BOOT_UART_BASE 0x87E028000000ll 126 #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 16666656 127 #define MARVELL_CONSOLE_BAUDRATE 115200 128 #define CONSOLE_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 129 130 /* eFUSE */ 131 #define PLAT_MARVELL_FUSF_FUSE_BASE 0x87E004000000ll 132 #define PLAT_MARVELL_FUSF_HUK_OFFSET (0x90) 133 134 #else 135 #error "Unknown platform flavor" 136 #endif 137 138 #define UART_BAUDRATE MARVELL_CONSOLE_BAUDRATE 139 #define CONSOLE_BAUDRATE UART_BAUDRATE 140 #define CONSOLE_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 141 142 #endif /*PLATFORM_CONFIG_H*/ 143