1 /* 2 * Copyright (c) 2017, Linaro Limited 3 * SPDX-License-Identifier: BSD-2-Clause 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <hi3798cv200.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 64 13 14 /* PL011 UART */ 15 #define CONSOLE_UART_BASE PL011_UART0_BASE 16 #define CONSOLE_BAUDRATE PL011_BAUDRATE 17 #define CONSOLE_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ 18 19 /* 20 * Poplar memory map 21 * 22 * Note: the physical address ranges below correspond to DRAM which is 23 * non-secure by default. Therefore, the terms TZDRAM and TZSRAM may not 24 * reflect the reality and only indicate areas that "would normally be" 25 * secure DRAM and secure SRAM in a more complete implementation. 26 * The memory map was defined like this for lack of better documentation. 27 * It is good enough for development/testing purposes. 28 * 29 * 0xFF00_0000 [DRAM2_LIMIT] 30 * other (devmem) 31 * 0xF000_0000 [DRAM2_BASE] 32 * 33 * 0x8000_0000 (0x4000_0000 for 1GB board) [DRAM0_LIMIT] 34 * u-boot + ree memory: 1144 MiB (144 MiB for 1GB board) 35 * 0x3700_0000 CONFIG_SYS_TEXT_BASE (u-boot) 36 * PLAT_POPLAR_NS_IMAGE_OFFSET (arm-tf) 37 * ramdisk: 76 MiB 38 * 0x3240_0000 39 * fdt: 2 MiB 40 * 0x3220_0000 41 * pxe file or script addr: 2 MiB 42 * 0x3200_0000 43 * kernel/android: 32 MiB 44 * 0x3000_0000 45 * ree memory: 696 MiB 46 * 0x0480_0000 CONFIG_SYS_LOAD_ADDR (defined in u-boot) 47 * other: 6 MiB 48 * 0x0420_0000 CONFIG_SYS_INIT_SP_ADDR (defined in u-boot) 49 * 0x0408_0000 KERNEL_TEXT_OFFSET (defined in u-boot) 50 * unused: 512 KiB 51 * 0x0400_0000 52 * 53 * 0x0400_0000 - 54 * TA RAM: 14 MiB | TZDRAM 55 * 0x0320_0000 - 56 * 57 * CFG_WITH_PAGER=n - 58 * TEE RAM: 2 MiB (TEE_RAM_VA_SIZE) | TZDRAM 59 * 0x0300_0000 [TZDRAM_BASE, TEE_LOAD_ADDR] - 60 * 61 * CFG_WITH_PAGER=y 62 * Unused 63 * 0x030A_0000 - 64 * TEE RAM: 640 KiB (TZSRAM_SIZE) | TZSRAM 65 * 0x0300_0000 [TZSRAM_BASE, TEE_LOAD_ADDR] - 66 * 67 * 0x0300_0000 [TZDRAM_BASE, TZSRAM_BASE, TEE_LOAD_ADDR] 68 * OP-TEE Future Use: 4 MiB 69 * 0x02C0_0000 70 * 71 * 0x02C0_0000 72 * Secure Data Path buffers: 4 MiB 73 * 0x0280_0000 [CFG_TEE_SDP_MEM_BASE] 74 * Shared memory: 4 MiB 75 * 0x0240_0000 76 * OP-TEE Future Use: 2 MiB 77 * 0x0220_0000 78 * 79 * 0x0220_0000 80 * unused: 64 KiB 81 * 0x021F_0000 l-loader limit (len/size set by poplar-l-loader.git) 82 * unused (cannot be used) 83 * 0x0210_0000 l-loader limit (max bootrom can accept) 84 * fip.bin load zone: 768 KiB 85 * 0x0204_0000 86 * bl31: 80 KiB 87 * 0x0202_A000 88 * bl2: 48 KiB 89 * 0x0201_E000 90 * bl1: 64 KiB 91 * 0x0200_E000 92 * l-loader text: 52 KiB 93 * 0x0200_1000 94 * unused 95 * 0x0200_0000 96 * TA virtual memory space 97 * 0x0000_0000 [DRAM0_BASE] 98 */ 99 #define DRAM0_BASE 0x00000000 100 #if (CFG_DRAM_SIZE_GB == 2) 101 #define DRAM0_SIZE 0x80000000 102 #elif (CFG_DRAM_SIZE_GB == 1) 103 #define DRAM0_SIZE 0x40000000 104 #else 105 #error Unsupported DRAM size 106 #endif 107 108 #define DRAM0_BASE_NSEC 0x04080000 109 #define DRAM0_SIZE_NSEC (DRAM0_SIZE - DRAM0_BASE_NSEC) 110 111 #define DRAM2_BASE 0xF0000000 112 #define DRAM2_SIZE 0x0F000000 113 114 #ifdef CFG_WITH_PAGER 115 116 #define TZSRAM_BASE 0x03000000 117 #define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE 118 119 #define TZDRAM_BASE 0x03200000 120 #define TZDRAM_SIZE (14 * 1024 * 1024) 121 122 #define TEE_RAM_START TZSRAM_BASE 123 #define TEE_RAM_PH_SIZE TZSRAM_SIZE 124 #define TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_PGDIR_SIZE) 125 #define TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_PGDIR_SIZE) 126 127 #else /* CFG_WITH_PAGER */ 128 129 #define TZDRAM_BASE 0x03000000 130 #define TZDRAM_SIZE (16 * 1024 * 1024) 131 132 #define TEE_RAM_START TZDRAM_BASE 133 #define TEE_RAM_PH_SIZE TEE_RAM_VA_SIZE 134 #define TA_RAM_START ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \ 135 CORE_MMU_PGDIR_SIZE) 136 137 #define TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE),\ 138 CORE_MMU_PGDIR_SIZE) 139 140 #endif /* CFG_WITH_PAGER */ 141 142 #define TEE_SHMEM_START 0x02400000 143 #define TEE_SHMEM_SIZE (4 * 1024 * 1024) 144 145 #define TEE_RAM_VA_SIZE (2 * 1024 * 1024) 146 147 #define TEE_LOAD_ADDR 0x03000000 /* BL32_BASE */ 148 149 #endif /* PLATFORM_CONFIG_H */ 150