1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
4  */
5 
6 #ifndef PLAT_ROCKCHIP_CRU_H
7 #define PLAT_ROCKCHIP_CRU_H
8 
9 #include <common.h>
10 #include <platform_config.h>
11 
12 #if defined(PLATFORM_FLAVOR_rk322x)
13 
14 enum plls_id {
15 	APLL_ID,
16 	DPLL_ID,
17 	CPLL_ID,
18 	GPLL_ID,
19 	PLL_END,
20 };
21 
22 #define CRU_SOFTRST_CON(i)		(0x110 + ((i) * 4))
23 #define CRU_MODE_CON			0x040
24 #define CRU_GLBRST_CFG_BASE		0x140
25 #define CRU_FSTRST_VAL_BASE		0x1f0
26 #define CRU_SNDRST_VAL_BASE		0x1f4
27 #define CRU_FSTRST_VAL			0xfdb9
28 #define CRU_SNDRST_VAL			0xeca8
29 #define PLLS_SLOW_MODE			0x11030000
30 
31 #define CORE_SOFT_RESET(core)		SHIFT_U32(0x100010, (core))
32 #define CORE_SOFT_RELEASE(core)		SHIFT_U32(0x100000, (core))
33 #define CORE_HELD_IN_RESET(core)	SHIFT_U32(0x000010, (core))
34 #define NONBOOT_CORES_SOFT_RESET	0x00e000e0
35 
36 #define CRU_CLKGATE_CON_CNT		16
37 #define CRU_CLKSEL_CON(i)		(0x044 + ((i) * 4))
38 #define CRU_CLKGATE_CON(i)		(0x0d0 + ((i) * 4))
39 #define CRU_PLL_CON0(pll)		((pll) * 0x0c + 0x0)
40 #define CRU_PLL_CON1(pll)		((pll) * 0x0c + 0x4)
41 #define CRU_PLL_CON2(pll)		((pll) * 0x0c + 0x8)
42 
43 #define PLL_LOCK			BIT(10)
44 #define PLL_POWER_UP			BITS_WITH_WMASK(0, 1, 13)
45 #define PLL_POWER_DOWN			BITS_WITH_WMASK(1, 1, 13)
46 
47 #define PLL_MODE_BIT(pll)		((pll) * 4)
48 #define PLL_MODE_MSK(pll)		BIT(PLL_MODE_BIT(pll))
49 #define PLL_SLOW_MODE(pll)		BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll))
50 #define PLL_NORM_MODE(pll)		BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll))
51 #endif
52 
53 #endif
54