1PLATFORM_FLAVOR ?= hihope_rzg2m
2
3include core/arch/arm/cpu/cortex-armv8-0.mk
4
5$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
6$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
7$(call force,CFG_SCIF,y)
8$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
9$(call force,CFG_CORE_ARM64_PA_BITS,36)
10
11# Disable core ASLR for two reasons:
12# 1. There is no source for ALSR seed, as RZ/G2 platform
13#    does not provide DTB to OP-TEE. Also, there is no
14#    publicly available documentation on integrated
15#    hardware RNG, so we can't use it either.
16# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR.
17$(call force,CFG_CORE_ASLR,n)
18
19ifeq ($(PLATFORM_FLAVOR),ek874)
20$(call force,CFG_TEE_CORE_NB_CORE,2)
21endif
22ifeq ($(PLATFORM_FLAVOR),hihope_rzg2m)
23$(call force,CFG_TEE_CORE_NB_CORE,6)
24# RZ/G2M have 6 cores for 2 clusters, but the number isn't contiguous.
25# One cluster has ids 0, 1, other has ids 3, 4, 5, 6.
26# CFG_CORE_CLUSTER_SHIFT will process to make the right numbering.
27$(call force,CFG_CORE_CLUSTER_SHIFT,1)
28endif
29ifeq ($(PLATFORM_FLAVOR),hihope_rzg2n)
30$(call force,CFG_TEE_CORE_NB_CORE,2)
31endif
32ifeq ($(PLATFORM_FLAVOR),hihope_rzg2h)
33$(call force,CFG_TEE_CORE_NB_CORE,8)
34endif
35
36CFG_TZDRAM_START ?= 0x44100000
37CFG_TZDRAM_SIZE ?= 0x03D00000
38CFG_TEE_RAM_VA_SIZE ?= 0x100000
39ifeq ($(CFG_ARM64_core),y)
40supported-ta-targets = ta_arm64
41endif
42
43CFG_DT ?= y
44