1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (c) 2016, Wind River Systems.
4 * Copyright (c) 2020, Linaro Limited
5 */
6
7/*
8 * Entry points for the A7 init.
9 *
10 * Assumptions:
11 * - No stack is available when these routines are called.
12 * - Each routine is called with return address in LR and
13 *   with ARM registers R0, R1, R2, R3 being scratchable.
14 */
15
16#include <arm32.h>
17#include <arm32_macros.S>
18#include <asm.S>
19#include <platform_config.h>
20
21.section .text
22.balign 4
23.code 32
24
25FUNC plat_cpu_reset_early , :
26	/*
27	 * SCR = 0x00000020
28	 * - FW: Disallow NSec to mask FIQ [bit4=0]
29	 * - AW: Allow NSec to manage Imprecise Abort [bit5=1]
30	 * - EA: Imprecise Abort trapped to Abort Mode [bit3=0]
31	 * - FIQ: In Sec world, FIQ trapped to FIQ Mode [bit2=0]
32	 * - IRQ: IRQ always trapped to IRQ Mode [bit1=0]
33	 * - NS: Secure World [bit0=0]
34	 */
35	mov r0, #SCR_AW
36	write_scr r0
37
38	mov_imm r0, 0x00000000
39	write_sctlr r0
40
41	/*
42	 * ACTRL = 0x00006040
43	 * - DDI: Disable dual issue [bit28=0]
44	 * - DDVM: Disable Distributed Virtual Memory transactions [bit15=0]
45	 * - L1PCTL: L1 Data prefetch control [bit14:13=2b11]
46	 * - L1RADIS: L1 Data Cache read-allocate mode disable [bit12=0]
47	 * - L2RADIS: L2 Data Cache read-allocate mode disable [bit11=0]
48	 * - DODMBS: Disable optimized data memory barrier behavior [bit10=0]
49	 * - SMP: Enables coherent requests to the processor [bit6=0]
50	 */
51	mov_imm r0, 0x00006040
52	write_actlr r0
53
54	/*
55	 * NSACR = 0x00000C00
56	 * - NS_SMP: Non-secure mode cannot change ACTRL.SMP (bit18=0)
57	 * - NSASEDIS/NSD32DIS/CP10/CP11: Non-secure mode can use SIMD/VFP
58	 *                                (bit15:14=2b00, bit11:10=2b11)
59	 */
60	mov_imm r0, 0x00000C00
61	write_nsacr r0
62
63	mov pc, lr
64END_FUNC plat_cpu_reset_early
65