1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2017, Schneider Electric 4 * Copyright (c) 2020, Linaro Limited 5 */ 6 7 #ifndef RZN1_TZ_H 8 #define RZN1_TZ_H 9 10 #include <util.h> 11 12 /* TZ config registers */ 13 #define FW_STATIC_TZA_INIT 0x4000C0D0 14 #define FW_STATIC_TZA_TARG 0x4000C0D4 15 16 /* TZ initiatior ports */ 17 #define TZ_INIT_CSB_SEC BIT(7) /* CoreSight AHB */ 18 #define TZ_INIT_CSA_SEC BIT(6) /* CoreSight AXI */ 19 #define TZ_INIT_YS_SEC BIT(5) /* Cortex-M3 System Bus interface */ 20 #define TZ_INIT_YC_SEC BIT(4) /* Cortex-M3 ICode interface */ 21 #define TZ_INIT_YD_SEC BIT(3) /* Cortex-M3 DCode interface */ 22 #define TZ_INIT_Z_SEC BIT(2) /* Packet Engine */ 23 #define TZ_INIT_I_SEC BIT(1) /* Peripheral Group */ 24 #define TZ_INIT_F_SEC BIT(0) /* Peripheral Group */ 25 26 /* TZ target ports */ 27 #define TZ_TARG_W_SEC BIT(14) /* RTC */ 28 #define TZ_TARG_PC_SEC BIT(9) /* DDR2/3 Controller */ 29 #define TZ_TARG_RA_SEC BIT(8) /* CoreSight */ 30 #define TZ_TARG_QB_SEC BIT(7) /* System Control */ 31 #define TZ_TARG_QA_SEC BIT(6) /* PG0 */ 32 #define TZ_TARG_NB_SEC BIT(5) /* Packet Engine */ 33 #define TZ_TARG_NA_SEC BIT(4) /* Public Key Processor */ 34 #define TZ_TARG_K_SEC BIT(3) /* Peripheral Group */ 35 #define TZ_TARG_J_SEC BIT(2) /* Peripheral Group */ 36 #define TZ_TARG_UB_SEC BIT(1) /* 2MB SRAM */ 37 #define TZ_TARG_UA_SEC BIT(0) /* 2MB SRAM */ 38 39 #endif /* RZN1_TZ_H */ 40