1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2017 Timesys Corporation. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 #include <sama5d2.h> 34 35 #define STACK_ALIGNMENT 64 36 37 #ifdef CFG_WITH_PAGER 38 #error "Pager not supported for platform sama5d2" 39 #endif 40 #ifdef CFG_WITH_LPAE 41 #error "LPAE not supported" 42 #endif 43 44 #define CONSOLE_UART_BASE AT91C_BASE_UART1 45 46 #define PL310_BASE (AT91C_BASE_L2CC) 47 #define SFR_BASE (AT91C_BASE_SFR) 48 49 /* 50 * PL310 Auxiliary Control Register 51 * 52 * I/Dcache prefetch enabled (bit29:28=2b11) 53 * NS can access interrupts (bit27=1) 54 * NS can lockdown cache lines (bit26=1) 55 * Round robin replacement policy (bit25=1) 56 * Force write allocated (default) 57 * Treats shared accesses (bit22=0, bit13=0) 58 * Parity disabled (bit21=0) 59 * Event monitor disabled (bit20=0) 60 * Platform flavor specific way config: 61 * - 16kb way size (bit19:17=3b001) 62 * Store buffer device limitation disabled (bit11=0) 63 * Cacheable accesses have high prio (bit10=0) 64 */ 65 #define PL310_AUX_CTRL_INIT 0x3E020000 66 67 /* 68 * PL310 Prefetch Control Register 69 * 70 * Double linefill enabled (bit30=1) 71 * I/D prefetch enabled (bit29:28=2b11) 72 * Prefetch drop enabled (bit24=1) 73 * Incr double linefill enable (bit23=1) 74 * Prefetch offset = 1 (bit4:0) 75 */ 76 #define PL310_PREFETCH_CTRL_INIT 0x71800001 77 78 /* 79 * PL310 Power Register 80 * 81 * Dynamic clock gating enabled 82 * Standby mode enabled 83 */ 84 #define PL310_POWER_CTRL_INIT 0x00000003 85 86 #endif /*PLATFORM_CONFIG_H*/ 87