1 /* SPDX-License-Identifier: BSD-Source-Code */ 2 /* 3 * Copyright (c) 2013, Atmel Corporation 4 * 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Atmel's name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef TZ_MATRIX_H 28 #define TZ_MATRIX_H 29 30 #define MATRIX_MCFG(n) (0x0000 + (n) * 4) /* Master Configuration Register */ 31 #define MATRIX_SCFG(n) (0x0040 + (n) * 4) /* Slave Configuration Register */ 32 #define MATRIX_PRAS(n) (0x0080 + (n) * 8) /* Priority Register A for Slave */ 33 #define MATRIX_PRBS(n) (0x0084 + (n) * 8) /* Priority Register B for Slave */ 34 35 #define MATRIX_MRCR 0x0100 /* Master Remap Control Register */ 36 #define MATRIX_MEIER 0x0150 /* Master Error Interrupt Enable Register */ 37 #define MATRIX_MEIDR 0x0154 /* Master Error Interrupt Disable Register */ 38 #define MATRIX_MEIMR 0x0158 /* Master Error Interrupt Mask Register */ 39 #define MATRIX_MESR 0x015c /* Master Error Status Register */ 40 41 /* Master n Error Address Register */ 42 #define MATRIX_MEAR(n) (0x0160 + (n) * 4) 43 44 #define MATRIX_WPMR 0x01E4 /* Write Protect Mode Register */ 45 #define MATRIX_WPSR 0x01E8 /* Write Protect Status Register */ 46 47 /* Security Slave n Register */ 48 #define MATRIX_SSR(n) (0x0200 + (n) * 4) 49 /* Security Area Split Slave n Register */ 50 #define MATRIX_SASSR(n) (0x0240 + (n) * 4) 51 /* Security Region Top Slave n Register */ 52 #define MATRIX_SRTSR(n) (0x0280 + (n) * 4) 53 54 /* Security Peripheral Select n Register */ 55 #define MATRIX_SPSELR(n) (0x02c0 + (n) * 4) 56 57 /**************************************************************************/ 58 /* Write Protect Mode Register (MATRIX_WPMR) */ 59 #define MATRIX_WPMR_WPEN (1 << 0) /* Write Protect Enable */ 60 #define MATRIX_WPMR_WPEN_DISABLE (0 << 0) 61 #define MATRIX_WPMR_WPEN_ENABLE (1 << 0) 62 #define MATRIX_WPMR_WPKEY (PASSWD << 8) /* Write Protect KEY */ 63 #define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154 << 8) 64 65 /* Security Slave Registers (MATRIX_SSRx) */ 66 #define MATRIX_LANSECH(n, bit) ((bit) << n) 67 #define MATRIX_LANSECH_S(n) (0x00 << n) 68 #define MATRIX_LANSECH_NS(n) (0x01 << n) 69 #define MATRIX_RDNSECH(n, bit) ((bit) << (n + 8)) 70 #define MATRIX_RDNSECH_S(n) (0x00 << (n + 8)) 71 #define MATRIX_RDNSECH_NS(n) (0x01 << (n + 8)) 72 #define MATRIX_WRNSECH(n, bit) ((bit) << (n + 16)) 73 #define MATRIX_WRNSECH_S(n) (0x00 << (n + 16)) 74 #define MATRIX_WRNSECH_NS(n) (0x01 << (n + 16)) 75 76 /* Security Areas Split Slave Registers (MATRIX_SASSRx) */ 77 #define MATRIX_SASPLIT(n, value) ((value) << (4 * n)) 78 #define MATRIX_SASPLIT_VALUE_4K 0x00 79 #define MATRIX_SASPLIT_VALUE_8K 0x01 80 #define MATRIX_SASPLIT_VALUE_16K 0x02 81 #define MATRIX_SASPLIT_VALUE_32K 0x03 82 #define MATRIX_SASPLIT_VALUE_64K 0x04 83 #define MATRIX_SASPLIT_VALUE_128K 0x05 84 #define MATRIX_SASPLIT_VALUE_256K 0x06 85 #define MATRIX_SASPLIT_VALUE_512K 0x07 86 #define MATRIX_SASPLIT_VALUE_1M 0x08 87 #define MATRIX_SASPLIT_VALUE_2M 0x09 88 #define MATRIX_SASPLIT_VALUE_4M 0x0a 89 #define MATRIX_SASPLIT_VALUE_8M 0x0b 90 #define MATRIX_SASPLIT_VALUE_16M 0x0c 91 #define MATRIX_SASPLIT_VALUE_32M 0x0d 92 #define MATRIX_SASPLIT_VALUE_64M 0x0e 93 #define MATRIX_SASPLIT_VALUE_128M 0x0f 94 95 /* Security Region Top Slave Registers (MATRIX_SRTSRx) */ 96 #define MATRIX_SRTOP(n, value) ((value) << (4 * n)) 97 #define MATRIX_SRTOP_VALUE_4K 0x00 98 #define MATRIX_SRTOP_VALUE_8K 0x01 99 #define MATRIX_SRTOP_VALUE_16K 0x02 100 #define MATRIX_SRTOP_VALUE_32K 0x03 101 #define MATRIX_SRTOP_VALUE_64K 0x04 102 #define MATRIX_SRTOP_VALUE_128K 0x05 103 #define MATRIX_SRTOP_VALUE_256K 0x06 104 #define MATRIX_SRTOP_VALUE_512K 0x07 105 #define MATRIX_SRTOP_VALUE_1M 0x08 106 #define MATRIX_SRTOP_VALUE_2M 0x09 107 #define MATRIX_SRTOP_VALUE_4M 0x0a 108 #define MATRIX_SRTOP_VALUE_8M 0x0b 109 #define MATRIX_SRTOP_VALUE_16M 0x0c 110 #define MATRIX_SRTOP_VALUE_32M 0x0d 111 #define MATRIX_SRTOP_VALUE_64M 0x0e 112 #define MATRIX_SRTOP_VALUE_128M 0x0f 113 114 #endif /* #ifndef TZ_MATRIX_H */ 115