1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #define DRAM0_BASE 0x80000000 10 #define DRAM0_SIZE 0x80000000 11 12 #if defined(PLATFORM_FLAVOR_dra7xx) || defined(PLATFORM_FLAVOR_am57xx) 13 14 /* Location of protected DDR on the DRA7xx platform */ 15 #define TZDRAM_BASE 0xbdb00000 16 #define TZDRAM_SIZE 0x01c00000 17 18 #ifdef CFG_WITH_PAGER 19 #define TZSRAM_BASE 0x40300000 20 #define TZSRAM_SIZE (256 * 1024) 21 #endif /* CFG_WITH_PAGER */ 22 23 24 #define UART1_BASE 0x4806A000 25 #define UART2_BASE 0x4806C000 26 #define UART3_BASE 0x48020000 27 28 #if defined(PLATFORM_FLAVOR_dra7xx) 29 #define CONSOLE_UART_BASE UART1_BASE 30 #elif defined(PLATFORM_FLAVOR_am57xx) 31 #define CONSOLE_UART_BASE UART3_BASE 32 #else 33 #error "Unknown platform flavor" 34 #endif 35 36 #define CONSOLE_BAUDRATE 115200 37 #define CONSOLE_UART_CLK_IN_HZ 48000000 38 39 #define SCU_BASE 0x48210000 40 #define GICC_OFFSET 0x2000 41 #define GICC_SIZE 0x1000 42 #define GICD_OFFSET 0x1000 43 #define GICD_SIZE 0x1000 44 #define GICC_BASE (SCU_BASE + GICC_OFFSET) 45 #define GICD_BASE (SCU_BASE + GICD_OFFSET) 46 47 #define WUGEN_MPU_BASE 0x48281000 48 #define WUGEN_MPU_SIZE 0x1000 49 50 #define SECRAM_BASE 0x40200000 51 #define SECRAM_SIZE 0x00100000 52 53 /* RNG */ 54 #define RNG_BASE 0x48090000 55 56 #elif defined(PLATFORM_FLAVOR_am43xx) 57 58 /* Location of protected DDR on the AM43xx platform */ 59 #define TZDRAM_BASE 0xbdb00000 60 #define TZDRAM_SIZE 0x01c00000 61 62 #define UART0_BASE 0x44E09000 63 #define UART1_BASE 0x48022000 64 #define UART2_BASE 0x48024000 65 #define UART3_BASE 0x481A6000 66 #define UART4_BASE 0x481A8000 67 #define UART5_BASE 0x481AA000 68 69 #define CONSOLE_UART_BASE UART0_BASE 70 #define CONSOLE_BAUDRATE 115200 71 #define CONSOLE_UART_CLK_IN_HZ 48000000 72 73 #define SCU_BASE 0x48240000 74 #define GICD_OFFSET 0x1000 75 #define GICD_SIZE 0x1000 76 #define GICC_OFFSET 0x0100 77 #define GICC_SIZE 0x0100 78 #define PL310_OFFSET 0x2000 79 #define PL310_SIZE 0x1000 80 #define GICD_BASE (SCU_BASE + GICD_OFFSET) 81 #define GICC_BASE (SCU_BASE + GICC_OFFSET) 82 #define PL310_BASE (SCU_BASE + PL310_OFFSET) 83 84 #define SECRAM_BASE 0x402F0000 85 #define SECRAM_SIZE 0x00100000 86 87 /* RNG */ 88 #define RNG_BASE 0x48310000 89 90 #else 91 #error "Unknown platform flavor" 92 #endif 93 94 /* Make stacks aligned to data cache line length */ 95 #define STACK_ALIGNMENT 64 96 97 #ifdef CFG_WITH_PAGER 98 /* 99 * Use TZSRAM for TEE, page out everything else to TZDRAM. 100 * +--------+----------+ 101 * | DRAM | SHMEM | 102 * +--------+----------+ 103 * | | TA_RAM | 104 * | TZDRAM +----------+ 105 * | | PAGE_RAM | 106 * +--------+----------+ 107 * | TZSRAM | TEE_RAM | 108 * +--------+----------+ 109 */ 110 #define TEE_RAM_VA_SIZE (1 * 1024 * 1024) 111 #define TEE_RAM_PH_SIZE TZSRAM_SIZE 112 #define TEE_RAM_START TZSRAM_BASE 113 #define TEE_LOAD_ADDR (TEE_RAM_START + 0x1000) 114 115 #else /* CFG_WITH_PAGER */ 116 /* 117 * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist, 118 * everything is in TZDRAM. 119 * +--------+---------+ 120 * | DRAM | SHMEM | 121 * +--------+---------+ 122 * | | TA_RAM | 123 * | TZDRAM +---------+ 124 * | | TEE_RAM | 125 * +--------+---------+ 126 */ 127 #define TEE_RAM_VA_SIZE (1 * 1024 * 1024) 128 #define TEE_RAM_PH_SIZE TEE_RAM_VA_SIZE 129 #define TEE_RAM_START TZDRAM_BASE 130 #define TEE_LOAD_ADDR TEE_RAM_START 131 132 #endif /* CFG_WITH_PAGER */ 133 134 #define TA_RAM_START ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \ 135 CORE_MMU_PGDIR_SIZE) 136 137 #define TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \ 138 CORE_MMU_PGDIR_SIZE) 139 140 /* Full GlobalPlatform test suite requires TEE_SHMEM_SIZE to be at least 2MB */ 141 #define TEE_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE) 142 #define TEE_SHMEM_SIZE (4 * 1024 * 1024) 143 144 #endif /*PLATFORM_CONFIG_H*/ 145