1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2017, Socionext Inc. 5 */ 6 7 #ifndef PLATFORM_CONFIG_H 8 #define PLATFORM_CONFIG_H 9 10 #include <mm/generic_ram_layout.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 /* GIC */ 16 #define GIC_BASE 0x5FE00000 17 #define GICD_OFFSET 0 18 #define GICC_OFFSET 0x80000 19 20 /* UART */ 21 #define UART_CH 0 22 #define UART_BASE 0x54006800 23 #define CONSOLE_UART_BASE (UART_BASE + 0x100 * UART_CH) 24 #define CONSOLE_BAUDRATE 115200 25 #define CONSOLE_UART_CLK_IN_HZ 58820000 26 27 /* 28 * UniPhier memory map 29 * 30 * 0xXXXX_XXXX 31 * Linux kernel and user space | DRAM#0-#x | Normal memory 32 * 0x8200_0000 [DRAM0_BASE] - - 33 * unused | | 34 * 0x81E8_0000 | | 35 * TA RAM: 13 MiB | TZDRAM | 36 * 0x8118_0000 | | Secure memory 37 * TEE RAM: 1 MiB (CFG_TEE_RAM_VA_SIZE) | | 38 * 0x8108_0000 [CFG_TZDRAM_START] - | 39 * BL31 runtime: 512 KiB | | 40 * 0x8100_0000 | - 41 * Shared memory: 2 MiB (CFG_SHMEM_SIZE) | | 42 * 0x80E0_0000 [CFG_SHMEM_START] | DRAM#0 | Normal memory 43 * reserved | | 44 * 0x8008_0000 | | 45 * BL2: 512 KiB | | 46 * 0x8000_0000 [CFG_DRAM0_BASE] - - 47 */ 48 49 #define DRAM0_BASE (CFG_DRAM0_BASE + CFG_DRAM0_RSV_SIZE) 50 #define DRAM0_SIZE (CFG_DRAM0_SIZE - CFG_DRAM0_RSV_SIZE) 51 52 #define CFG_TEE_LOAD_ADDR CFG_TZDRAM_START 53 54 #endif /* PLATFORM_CONFIG_H */ 55