1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) Foundries Ltd. 2022 - All Rights Reserved 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define CACHELINE_LEN 64 13 #define STACK_ALIGNMENT CACHELINE_LEN 14 15 #if defined(PLATFORM_FLAVOR_generic) 16 17 #define PLM_RTCA 0xF2014000 18 #define PLM_RTCA_LEN 0x1000 19 20 #define GIC_BASE 0xF9000000 21 #define UART0_BASE 0xFF000000 22 #define UART1_BASE 0xFF010000 23 24 #define IT_UART0 50 25 #define IT_UART1 51 26 27 #define UART0_CLK_IN_HZ 100000000 28 #define UART1_CLK_IN_HZ 100000000 29 #define CONSOLE_UART_BASE UART0_BASE 30 #define IT_CONSOLE_UART IT_UART0 31 #define CONSOLE_UART_CLK_IN_HZ UART0_CLK_IN_HZ 32 33 #define DRAM0_BASE 0 34 #define DRAM0_SIZE 0x80000000 35 36 #ifdef ARM64 37 /* DDR High area base is only available when compiling for 64 bits */ 38 #define DRAM1_BASE 0x800000000 39 #define DRAM1_SIZE 0x180000000 40 #define DRAM2_BASE 0x50000000000 41 #define DRAM2_SIZE 0x200000000 42 #endif 43 44 #define GICD_OFFSET 0 45 #define GICC_OFFSET 0x40000 46 47 #else 48 #error "Unknown platform flavor" 49 #endif 50 51 #ifdef CFG_TEE_LOAD_ADDR 52 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR 53 #else 54 #define TEE_LOAD_ADDR TEE_RAM_START 55 #endif 56 57 #ifndef UART_BAUDRATE 58 #define UART_BAUDRATE 115200 59 #endif 60 #ifndef CONSOLE_BAUDRATE 61 #define CONSOLE_BAUDRATE UART_BAUDRATE 62 #endif 63 64 #endif /* PLATFORM_CONFIG_H */ 65