1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2016-2020, Linaro Limited
4 * Copyright (c) 2014, STMicroelectronics International N.V.
5 */
6
7 #include <arm.h>
8 #include <console.h>
9 #include <drivers/gic.h>
10 #include <drivers/pl011.h>
11 #include <drivers/tpm2_mmio.h>
12 #include <drivers/tpm2_ptp_fifo.h>
13 #include <drivers/tzc400.h>
14 #include <initcall.h>
15 #include <keep.h>
16 #include <kernel/boot.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/notif.h>
20 #include <kernel/panic.h>
21 #include <kernel/spinlock.h>
22 #include <kernel/tee_time.h>
23 #include <mm/core_memprot.h>
24 #include <mm/core_mmu.h>
25 #include <platform_config.h>
26 #include <sm/psci.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <trace.h>
30
31 static struct gic_data gic_data __nex_bss;
32 static struct pl011_data console_data __nex_bss;
33
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
35 #if defined(CFG_DRIVERS_TPM2_MMIO)
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TPM2_BASE, TPM2_REG_SIZE);
37 #endif
38 #if defined(PLATFORM_FLAVOR_fvp)
39 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE);
40 #endif
41 #if defined(PLATFORM_FLAVOR_qemu_virt)
42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
43 #endif
44 #ifdef DRAM0_BASE
45 register_ddr(DRAM0_BASE, DRAM0_SIZE);
46 #endif
47 #ifdef DRAM1_BASE
48 register_ddr(DRAM1_BASE, DRAM1_SIZE);
49 #endif
50
51 #ifdef GIC_BASE
52
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
55
main_init_gic(void)56 void main_init_gic(void)
57 {
58 #if defined(CFG_WITH_ARM_TRUSTED_FW)
59 /* On ARMv8, GIC configuration is initialized in ARM-TF */
60 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET,
61 GIC_BASE + GICD_OFFSET);
62 #else
63 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
64 #endif
65 itr_init(&gic_data.chip);
66 }
67
68 #if !defined(CFG_WITH_ARM_TRUSTED_FW)
main_secondary_init_gic(void)69 void main_secondary_init_gic(void)
70 {
71 gic_cpu_init(&gic_data);
72 }
73 #endif
74
75 #endif
76
itr_core_handler(void)77 void itr_core_handler(void)
78 {
79 gic_it_handle(&gic_data);
80 }
81
console_init(void)82 void console_init(void)
83 {
84 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
85 CONSOLE_BAUDRATE);
86 register_serial_console(&console_data.chip);
87 }
88
89 #if defined(IT_CONSOLE_UART) && !defined(CFG_VIRTUALIZATION) && \
90 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2))
91 /*
92 * This cannot be enabled with TF-A and GICv3 because TF-A then need to
93 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently
94 * there's no way of TF-A to know which interrupts that OP-TEE will serve.
95 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it
96 * will hang in EL3 since the interrupt will just be delivered again and
97 * again.
98 */
99
read_console(void)100 static void read_console(void)
101 {
102 struct serial_chip *cons = &console_data.chip;
103
104 if (!cons->ops->getchar || !cons->ops->have_rx_data)
105 return;
106
107 while (cons->ops->have_rx_data(cons)) {
108 int ch __maybe_unused = cons->ops->getchar(cons);
109
110 DMSG("got 0x%x", ch);
111 }
112 }
113
console_itr_cb(struct itr_handler * h __maybe_unused)114 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused)
115 {
116 if (notif_async_is_started()) {
117 /*
118 * Asynchronous notifications are enabled, lets read from
119 * uart in the bottom half instead.
120 */
121 itr_disable(IT_CONSOLE_UART);
122 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF);
123 } else {
124 read_console();
125 }
126 return ITRR_HANDLED;
127 }
128
129 static struct itr_handler console_itr = {
130 .it = IT_CONSOLE_UART,
131 .flags = ITRF_TRIGGER_LEVEL,
132 .handler = console_itr_cb,
133 };
134 DECLARE_KEEP_PAGER(console_itr);
135
atomic_console_notif(struct notif_driver * ndrv __unused,enum notif_event ev __maybe_unused)136 static void atomic_console_notif(struct notif_driver *ndrv __unused,
137 enum notif_event ev __maybe_unused)
138 {
139 DMSG("Asynchronous notifications started, event %d", (int)ev);
140 }
141 DECLARE_KEEP_PAGER(atomic_console_notif);
142
yielding_console_notif(struct notif_driver * ndrv __unused,enum notif_event ev)143 static void yielding_console_notif(struct notif_driver *ndrv __unused,
144 enum notif_event ev)
145 {
146 switch (ev) {
147 case NOTIF_EVENT_DO_BOTTOM_HALF:
148 read_console();
149 itr_enable(IT_CONSOLE_UART);
150 break;
151 case NOTIF_EVENT_STOPPED:
152 DMSG("Asynchronous notifications stopped");
153 itr_enable(IT_CONSOLE_UART);
154 break;
155 default:
156 EMSG("Unknown event %d", (int)ev);
157 }
158 }
159
160 struct notif_driver console_notif = {
161 .atomic_cb = atomic_console_notif,
162 .yielding_cb = yielding_console_notif,
163 };
164
init_console_itr(void)165 static TEE_Result init_console_itr(void)
166 {
167 itr_add(&console_itr);
168 itr_enable(IT_CONSOLE_UART);
169 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF))
170 notif_register_driver(&console_notif);
171 return TEE_SUCCESS;
172 }
173 driver_init(init_console_itr);
174 #endif
175
176 #if defined(CFG_DRIVERS_TPM2_MMIO)
init_tpm2(void)177 static TEE_Result init_tpm2(void)
178 {
179 enum tpm2_result res = TPM2_OK;
180
181 res = tpm2_mmio_init(TPM2_BASE);
182 if (res) {
183 EMSG("Failed to initialize TPM2 MMIO");
184 return TEE_ERROR_GENERIC;
185 }
186
187 DMSG("TPM2 Chip initialized");
188
189 return TEE_SUCCESS;
190 }
191 driver_init(init_tpm2);
192 #endif /* defined(CFG_DRIVERS_TPM2_MMIO) */
193
194 #ifdef CFG_TZC400
195 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
196
init_tzc400(void)197 static TEE_Result init_tzc400(void)
198 {
199 void *va;
200
201 DMSG("Initializing TZC400");
202
203 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE);
204 if (!va) {
205 EMSG("TZC400 not mapped");
206 panic();
207 }
208
209 tzc_init((vaddr_t)va);
210 tzc_dump_state();
211
212 return TEE_SUCCESS;
213 }
214
215 service_init(init_tzc400);
216 #endif /*CFG_TZC400*/
217
218 #if defined(PLATFORM_FLAVOR_qemu_virt)
release_secondary_early_hpen(size_t pos)219 static void release_secondary_early_hpen(size_t pos)
220 {
221 struct mailbox {
222 uint64_t ep;
223 uint64_t hpen[];
224 } *mailbox;
225
226 if (cpu_mmu_enabled())
227 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC,
228 SECRAM_COHERENT_SIZE);
229 else
230 mailbox = (void *)SECRAM_BASE;
231
232 if (!mailbox)
233 panic();
234
235 mailbox->ep = TEE_LOAD_ADDR;
236 dsb_ishst();
237 mailbox->hpen[pos] = 1;
238 dsb_ishst();
239 sev();
240 }
241
psci_cpu_on(uint32_t core_id,uint32_t entry,uint32_t context_id)242 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id)
243 {
244 size_t pos = get_core_pos_mpidr(core_id);
245 static bool core_is_released[CFG_TEE_CORE_NB_CORE];
246
247 if (!pos || pos >= CFG_TEE_CORE_NB_CORE)
248 return PSCI_RET_INVALID_PARAMETERS;
249
250 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry);
251
252 if (core_is_released[pos]) {
253 EMSG("core %zu already released", pos);
254 return PSCI_RET_DENIED;
255 }
256 core_is_released[pos] = true;
257
258 boot_set_core_ns_entry(pos, entry, context_id);
259 release_secondary_early_hpen(pos);
260
261 return PSCI_RET_SUCCESS;
262 }
263 #endif /*PLATFORM_FLAVOR_qemu_virt*/
264