1PLATFORM_FLAVOR ?= zcu102
2
3include core/arch/arm/cpu/cortex-armv8-0.mk
4
5$(call force,CFG_TEE_CORE_NB_CORE,4)
6$(call force,CFG_CDNS_UART,y)
7$(call force,CFG_GIC,y)
8$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
9$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
10
11# Disable core ASLR for two reasons:
12# 1. There is no source for ALSR seed, as ATF does not provide a
13#    DTB to OP-TEE. Hardware RNG is also not currently supported.
14# 2. OP-TEE does not boot with enabled CFG_CORE_ASLR.
15$(call force,CFG_CORE_ASLR,n)
16
17ifeq ($(CFG_ARM64_core),y)
18# ZynqMP supports up to 40 bits of physical addresses
19CFG_CORE_ARM64_PA_BITS ?= 40
20else
21$(call force,CFG_ARM32_core,y)
22endif
23
24ifneq (,$(filter $(PLATFORM_FLAVOR),zcu102 zcu104 zcu106 zc1751_dc1 zc1751_dc2))
25
26CFG_UART_BASE ?= UART0_BASE
27CFG_UART_IT ?= IT_UART0
28CFG_UART_CLK_HZ ?= UART0_CLK_IN_HZ
29
30# ZCU102 features 4 GiB of DDR
31ifeq ($(CFG_ARM64_core),y)
32CFG_DDR_SIZE ?= 0x100000000
33else
34# On 32 bit build limit to 2 GiB of RAM
35CFG_DDR_SIZE ?= 0x80000000
36endif
37endif
38
39ifneq (,$(filter $(PLATFORM_FLAVOR),ultra96))
40
41CFG_UART_BASE ?= UART1_BASE
42CFG_UART_IT ?= IT_UART1
43CFG_UART_CLK_HZ ?= UART1_CLK_IN_HZ
44
45# Ultra96 features 2 GiB of DDR
46CFG_DDR_SIZE ?= 0x80000000
47endif
48
49# By default use DT address as specified by Xilinx
50CFG_DT_ADDR ?= 0x100000
51
52CFG_TZDRAM_START ?= 0x60000000
53CFG_TZDRAM_SIZE  ?= 0x10000000
54CFG_SHMEM_START  ?= 0x70000000
55CFG_SHMEM_SIZE   ?= 0x10000000
56
57CFG_WITH_STATS ?= y
58CFG_CRYPTO_WITH_CE ?= y
59
60# Enable use of User AES eFuse as device key instead of PUF.
61# This is needed when images are encrypted with AES eFuse device key (AES_KEY).
62CFG_ZYNQMP_HUK_AES_EFUSE ?= n
63
64# Configures bitmask which user eFuses should be included in HUK generation.
65# Used when (part of) user eFuses are used for HUK seed (i.e. programmed with
66# good random values).
67# Bit 0 means eFuse USER_0, bit 1 for eFuse USER 1 and so on.
68CFG_ZYNQMP_HUK_USER_EFUSE_MASK ?= 0
69
70CFG_ZYNQMP_PM ?= $(CFG_ARM64_core)
71
72ifeq ($(CFG_RPMB_FS),y)
73$(call force,CFG_ZYNQMP_HUK,y,Mandated by CFG_RPMB_FS)
74endif
75
76ifeq ($(CFG_ZYNQMP_HUK),y)
77$(call force,CFG_ZYNQMP_CSU_AES,y,Mandated by CFG_ZYNQMP_HUK)
78ifneq ($(CFG_ZYNQMP_HUK_AES_EFUSE),y)
79$(call force,CFG_ZYNQMP_CSU_PUF,y,Mandated by CFG_ZYNQMP_HUK)
80endif
81endif
82
83ifeq ($(CFG_ZYNQMP_CSU_AES),y)
84$(call force,CFG_ZYNQMP_CSUDMA,y,Mandated by CFG_ZYNQMP_CSU_AES)
85$(call force,CFG_DT,y,Mandated by CFG_ZYNQMP_CSU_AES)
86endif
87
88ifneq (,$(filter y, $(CFG_ZYNQMP_CSU_PUF) $(CFG_ZYNQMP_CSUDMA) $(CFG_ZYNQMP_CSU_AES)))
89$(call force,CFG_ZYNQMP_CSU,y,Mandated by CFG_ZYNQMP_CSU* clients)
90endif
91