1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright 2022 Microchip
4 *
5 * Driver for AT91 RTC
6 */
7
8 #include <assert.h>
9 #include <drivers/atmel_rtc.h>
10 #include <drivers/rtc.h>
11 #include <io.h>
12 #include <kernel/dt.h>
13 #include <matrix.h>
14 #include <mm/core_memprot.h>
15 #include <sama5d2.h>
16
17 #define RTC_VAL(reg, val) (((val) >> RTC_## reg ## _SHIFT) & \
18 RTC_## reg ##_MASK)
19
20 #define RTC_SET_VAL(reg, val) SHIFT_U32((val) & RTC_## reg ##_MASK, \
21 RTC_## reg ## _SHIFT)
22
23 #define RTC_CR 0x0
24 #define RTC_CR_UPDCAL BIT(1)
25 #define RTC_CR_UPDTIM BIT(0)
26
27 #define RTC_MR 0x4
28 #define RTC_MR_HR_MODE BIT(0)
29 #define RTC_MR_PERSIAN BIT(1)
30 #define RTC_MR_UTC BIT(2)
31 #define RTC_MR_NEGPPM BIT(4)
32 #define RTC_MR_CORR_SHIFT 8
33 #define RTC_MR_CORR_MASK GENMASK_32(6, 0)
34 #define RTC_MR_CORR(val) RTC_VAL(val, MR_CORR)
35 #define RTC_MR_HIGHPPM BIT(15)
36
37 #define RTC_TIMR 0x8
38 #define RTC_CALR 0xC
39
40 #define RTC_SR 0x18
41 #define RTC_SR_ACKUPD BIT(0)
42 #define RTC_SR_SEC BIT(2)
43
44 #define RTC_SCCR 0x1C
45 #define RTC_SCCR_ACKCLR BIT(0)
46 #define RTC_SCCR_SECCLR BIT(2)
47
48 #define RTC_VER 0x2C
49 #define RTC_VER_NVTIM BIT(0)
50 #define RTC_VER_NVCAL BIT(1)
51
52 #define RTC_TSTR0 0xB0
53 #define RTC_TSDR0 0xB4
54
55 #define RTC_TSSR0 0xB8
56 #define RTC_TSSR_DET_OFFSET 16
57 #define RTC_TSSR_DET_COUNT 8
58 #define RTC_TSSR_TST_PIN BIT(2)
59 #define RTC_TSSR_JTAG BIT(3)
60
61 /* Layout of Time registers */
62 #define RTC_TIME_BACKUP BIT(31)
63 #define RTC_TIME_HOUR_SHIFT 16
64 #define RTC_TIME_HOUR_MASK GENMASK_32(5, 0)
65 #define RTC_TIME_MIN_SHIFT 8
66 #define RTC_TIME_MIN_MASK GENMASK_32(6, 0)
67 #define RTC_TIME_SEC_SHIFT 0
68 #define RTC_TIME_SEC_MASK GENMASK_32(6, 0)
69
70 /* Layout of Calendar registers */
71 #define RTC_CAL_DATE_SHIFT 24
72 #define RTC_CAL_DATE_MASK GENMASK_32(5, 0)
73 #define RTC_CAL_DAY_SHIFT 21
74 #define RTC_CAL_DAY_MASK GENMASK_32(2, 0)
75 #define RTC_CAL_MONTH_SHIFT 16
76 #define RTC_CAL_MONTH_MASK GENMASK_32(4, 0)
77 #define RTC_CAL_YEAR_SHIFT 8
78 #define RTC_CAL_YEAR_MASK GENMASK_32(7, 0)
79 #define RTC_CAL_CENT_SHIFT 0
80 #define RTC_CAL_CENT_MASK GENMASK_32(6, 0)
81
82 #define ATMEL_RTC_CORR_DIVIDEND 3906000
83 #define ATMEL_RTC_CORR_LOW_RATIO 20
84
85 static vaddr_t rtc_base;
86
bcd_decode(uint8_t dcb_val)87 static uint8_t bcd_decode(uint8_t dcb_val)
88 {
89 return (dcb_val & 0xF) + (dcb_val >> 4) * 10;
90 }
91
bcd_encode(uint32_t value)92 static uint8_t bcd_encode(uint32_t value)
93 {
94 return ((value / 10) << 4) + value % 10;
95 }
96
atmel_rtc_read(unsigned int offset)97 static uint32_t atmel_rtc_read(unsigned int offset)
98 {
99 return io_read32(rtc_base + offset);
100 }
101
atmel_rtc_write(unsigned int offset,uint32_t val)102 static void atmel_rtc_write(unsigned int offset, uint32_t val)
103 {
104 return io_write32(rtc_base + offset, val);
105 }
106
atmel_decode_date(unsigned int time_reg,unsigned int cal_reg,struct optee_rtc_time * tm)107 static void atmel_decode_date(unsigned int time_reg, unsigned int cal_reg,
108 struct optee_rtc_time *tm)
109 {
110 uint32_t time = 0;
111 uint32_t date = 0;
112
113 /* Must read twice in case it changes */
114 do {
115 time = atmel_rtc_read(time_reg);
116 date = atmel_rtc_read(cal_reg);
117 } while ((time != atmel_rtc_read(time_reg)) ||
118 (date != atmel_rtc_read(cal_reg)));
119
120 tm->tm_wday = bcd_decode(RTC_VAL(CAL_DAY, date)) - 1;
121 tm->tm_mday = bcd_decode(RTC_VAL(CAL_DATE, date));
122 tm->tm_mon = bcd_decode(RTC_VAL(CAL_MONTH, date)) - 1;
123 tm->tm_year = bcd_decode(RTC_VAL(CAL_CENT, date)) * 100;
124 tm->tm_year += bcd_decode(RTC_VAL(CAL_YEAR, date));
125
126 tm->tm_hour = bcd_decode(RTC_VAL(TIME_HOUR, time));
127 tm->tm_min = bcd_decode(RTC_VAL(TIME_MIN, time));
128 tm->tm_sec = bcd_decode(RTC_VAL(TIME_SEC, time));
129 }
130
atmel_rtc_get_time(struct rtc * rtc __unused,struct optee_rtc_time * tm)131 static TEE_Result atmel_rtc_get_time(struct rtc *rtc __unused,
132 struct optee_rtc_time *tm)
133 {
134 atmel_decode_date(RTC_TIMR, RTC_CALR, tm);
135
136 return TEE_SUCCESS;
137 }
138
atmel_rtc_get_tamper_timestamp(struct optee_rtc_time * tm)139 TEE_Result atmel_rtc_get_tamper_timestamp(struct optee_rtc_time *tm)
140 {
141 if (!rtc_base)
142 return TEE_ERROR_NOT_SUPPORTED;
143
144 atmel_decode_date(RTC_TSTR0, RTC_TSDR0, tm);
145
146 return TEE_SUCCESS;
147 }
148
atmel_rtc_set_time(struct rtc * rtc __unused,struct optee_rtc_time * tm)149 static TEE_Result atmel_rtc_set_time(struct rtc *rtc __unused,
150 struct optee_rtc_time *tm)
151 {
152 uint32_t cr = 0;
153 uint32_t sr = 0;
154 uint32_t err = 0;
155
156 /* First, wait for UPDCAL/UPDTIM to be 0 */
157 do {
158 cr = atmel_rtc_read(RTC_CR);
159 } while (cr & (RTC_CR_UPDCAL | RTC_CR_UPDTIM));
160
161 /* Stop Time/Calendar for update */
162 atmel_rtc_write(RTC_CR, cr | RTC_CR_UPDCAL | RTC_CR_UPDTIM);
163
164 do {
165 sr = atmel_rtc_read(RTC_SR);
166 } while (!(sr & RTC_SR_ACKUPD));
167
168 atmel_rtc_write(RTC_SCCR, RTC_SCCR_ACKCLR);
169
170 atmel_rtc_write(RTC_TIMR,
171 RTC_SET_VAL(TIME_SEC, bcd_encode(tm->tm_sec)) |
172 RTC_SET_VAL(TIME_MIN, bcd_encode(tm->tm_min)) |
173 RTC_SET_VAL(TIME_HOUR, bcd_encode(tm->tm_hour)));
174
175 atmel_rtc_write(RTC_CALR,
176 RTC_SET_VAL(CAL_CENT,
177 bcd_encode(tm->tm_year / 100)) |
178 RTC_SET_VAL(CAL_YEAR, bcd_encode(tm->tm_year % 100)) |
179 RTC_SET_VAL(CAL_MONTH, bcd_encode(tm->tm_mon + 1)) |
180 RTC_SET_VAL(CAL_DAY, bcd_encode(tm->tm_wday + 1)) |
181 RTC_SET_VAL(CAL_DATE, bcd_encode(tm->tm_mday)));
182
183 err = atmel_rtc_read(RTC_VER);
184 if (err) {
185 if (err & RTC_VER_NVTIM)
186 DMSG("Invalid time programmed");
187 if (err & RTC_VER_NVCAL)
188 DMSG("Invalid date programmed");
189
190 return TEE_ERROR_BAD_PARAMETERS;
191 }
192
193 /* Restart Time/Calendar */
194 atmel_rtc_write(RTC_CR, cr);
195
196 return TEE_SUCCESS;
197 }
198
atmel_rtc_get_offset(struct rtc * rtc __unused,long * offset)199 static TEE_Result atmel_rtc_get_offset(struct rtc *rtc __unused, long *offset)
200 {
201 uint32_t mr = atmel_rtc_read(RTC_MR);
202 long val = RTC_VAL(MR_CORR, mr);
203
204 if (!val) {
205 *offset = 0;
206 return TEE_SUCCESS;
207 }
208
209 val++;
210
211 if (!(mr & RTC_MR_HIGHPPM))
212 val *= ATMEL_RTC_CORR_LOW_RATIO;
213
214 val = UDIV_ROUND_NEAREST(ATMEL_RTC_CORR_DIVIDEND, val);
215
216 if (!(mr & RTC_MR_NEGPPM))
217 val = -val;
218
219 *offset = val;
220
221 return TEE_SUCCESS;
222 }
223
atmel_rtc_set_offset(struct rtc * rtc __unused,long offset)224 static TEE_Result atmel_rtc_set_offset(struct rtc *rtc __unused, long offset)
225 {
226 long corr = 0;
227 uint32_t mr = 0;
228
229 if (offset > ATMEL_RTC_CORR_DIVIDEND / 2)
230 return TEE_ERROR_BAD_PARAMETERS;
231 if (offset < -ATMEL_RTC_CORR_DIVIDEND / 2)
232 return TEE_ERROR_BAD_PARAMETERS;
233
234 mr = atmel_rtc_read(RTC_MR);
235 mr &= ~(RTC_MR_NEGPPM | RTC_MR_CORR_MASK | RTC_MR_HIGHPPM);
236
237 if (offset > 0)
238 mr |= RTC_MR_NEGPPM;
239 else
240 offset = -offset;
241
242 /* offset less than 764 ppb, disable correction */
243 if (offset < 764) {
244 atmel_rtc_write(RTC_MR, mr & ~RTC_MR_NEGPPM);
245
246 return TEE_SUCCESS;
247 }
248
249 /*
250 * 29208 ppb is the perfect cutoff between low range and high range
251 * low range values are never better than high range value after that.
252 */
253 if (offset < 29208) {
254 corr = UDIV_ROUND_NEAREST(ATMEL_RTC_CORR_DIVIDEND,
255 offset * ATMEL_RTC_CORR_LOW_RATIO);
256 } else {
257 corr = UDIV_ROUND_NEAREST(ATMEL_RTC_CORR_DIVIDEND, offset);
258 mr |= RTC_MR_HIGHPPM;
259 }
260
261 corr = MIN(corr, 128);
262
263 mr |= ((corr - 1) & RTC_MR_CORR_MASK) << RTC_MR_CORR_SHIFT;
264
265 atmel_rtc_write(RTC_MR, mr);
266
267 return TEE_SUCCESS;
268 }
269
270 static const struct rtc_ops atmel_rtc_ops = {
271 .get_time = atmel_rtc_get_time,
272 .set_time = atmel_rtc_set_time,
273 .get_offset = atmel_rtc_get_offset,
274 .set_offset = atmel_rtc_set_offset,
275 };
276
277 static struct rtc atmel_rtc = {
278 .ops = &atmel_rtc_ops,
279 .range_min = { 1900, 1, 1, 0, 0, 0, 0 },
280 .range_max = { 2099, 12, 31, 23, 59, 59, 0 },
281 };
282
atmel_rtc_probe(const void * fdt,int node,const void * compat_data __unused)283 static TEE_Result atmel_rtc_probe(const void *fdt, int node,
284 const void *compat_data __unused)
285 {
286 size_t size = 0;
287
288 if (rtc_base)
289 return TEE_ERROR_GENERIC;
290
291 if (_fdt_get_status(fdt, node) != DT_STATUS_OK_SEC)
292 return TEE_ERROR_BAD_PARAMETERS;
293
294 matrix_configure_periph_secure(AT91C_ID_SYS);
295
296 if (dt_map_dev(fdt, node, &rtc_base, &size, DT_MAP_AUTO) < 0)
297 return TEE_ERROR_GENERIC;
298
299 atmel_rtc_write(RTC_CR, 0);
300 /* Enable 24 hours Gregorian mode (this is a clear bits operation !) */
301 io_clrbits32(rtc_base + RTC_MR, RTC_MR_PERSIAN | RTC_MR_UTC |
302 RTC_MR_HR_MODE);
303
304 rtc_register(&atmel_rtc);
305
306 return TEE_SUCCESS;
307 }
308
309 static const struct dt_device_match atmel_rtc_match_table[] = {
310 { .compatible = "atmel,sama5d2-rtc" },
311 { }
312 };
313
314 DEFINE_DT_DRIVER(atmel_rtc_dt_driver) = {
315 .name = "atmel_rtc",
316 .type = DT_DRIVER_NOTYPE,
317 .match_table = atmel_rtc_match_table,
318 .probe = atmel_rtc_probe,
319 };
320
321