1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd.
4 */
5 #include <arm.h>
6 #include <drivers/imx_i2c.h>
7 #include <initcall.h>
8 #include <io.h>
9 #include <kernel/boot.h>
10 #include <kernel/delay.h>
11 #include <kernel/dt.h>
12 #include <libfdt.h>
13 #include <mm/core_memprot.h>
14 #include <mm/core_mmu.h>
15 #include <platform_config.h>
16 #include <stdlib.h>
17 #include <trace.h>
18 #include <util.h>
19
20 #define I2C_CLK_RATE 24000000 /* Bits per second */
21
22 /* Utility macros (__x identifies the bus [1 .. 3]) */
23 #define I2C_CFG_SCL(__x) (IOMUXC_I2C1_SCL_CFG_OFF + ((__x) - 1) * 0x8)
24 #define I2C_CFG_SDA(__x) (IOMUXC_I2C1_SDA_CFG_OFF + ((__x) - 1) * 0x8)
25 #define I2C_MUX_SCL(__x) (IOMUXC_I2C1_SCL_MUX_OFF + ((__x) - 1) * 0x8)
26 #define I2C_MUX_SDA(__x) (IOMUXC_I2C1_SDA_MUX_OFF + ((__x) - 1) * 0x8)
27 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MP) || \
28 defined(CFG_MX8MN)
29 /* IOMUX */
30 #define I2C_INP_SCL(__x) 0 /* Not implemented */
31 #define I2C_INP_SDA(__x) 0 /* Not implemented */
32 #define I2C_INP_VAL(__x) 0 /* Not implemented */
33 #define I2C_MUX_VAL(__x) 0x010
34 #define I2C_CFG_VAL(__x) 0x1c3
35 /* Clock */
36 #define I2C_CLK_CGRBM(__x) 0 /* Not implemented */
37 #define I2C_CLK_CGR6BM(__x) 0
38 #define I2C_CLK_CGR(__x) CCM_CCRG_I2C##__x
39 #elif defined(CFG_MX6ULL)
40 /* IOMUX */
41 #define I2C_INP_SCL(__x) (IOMUXC_I2C1_SCL_INP_OFF + ((__x) - 1) * 0x8)
42 #define I2C_INP_SDA(__x) (IOMUXC_I2C1_SDA_INP_OFF + ((__x) - 1) * 0x8)
43 #define I2C_INP_VAL(__x) (((__x) == 1) ? 0x1 : 0x2)
44 #define I2C_MUX_VAL(__x) 0x012
45 #define I2C_CFG_VAL(__x) 0x1b8b0
46 /* Clock */
47 #define I2C_CLK_CGRBM(__x) BM_CCM_CCGR2_I2C##__x##_SERIAL
48 #define I2C_CLK_CGR6BM(__x) BM_CCM_CCGR6_I2C##__x##_SERIAL
49 #define I2C_CLK_CGR(__x) (((__x) == 4) ? CCM_CCGR6 : CCM_CCGR2)
50 #else
51 #error IMX_I2C driver not supported on this platform
52 #endif
53
54 #if !defined(CFG_MX8MP)
55 static struct io_pa_va i2c_bus[4] = {
56 #if !defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY)
57 #if defined(I2C1_BASE)
58 [0] = { .pa = I2C1_BASE, },
59 #endif
60 #if defined(I2C2_BASE)
61 [1] = { .pa = I2C2_BASE, },
62 #endif
63 #if defined(I2C3_BASE)
64 [2] = { .pa = I2C3_BASE, },
65 #endif
66 #if defined(I2C4_BASE)
67 [3] = { .pa = I2C4_BASE, },
68 #endif
69 #endif
70 };
71 #else
72 static struct io_pa_va i2c_bus[6] = {
73 #if !defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY)
74 #if defined(I2C1_BASE)
75 [0] = { .pa = I2C1_BASE, },
76 #endif
77 #if defined(I2C2_BASE)
78 [1] = { .pa = I2C2_BASE, },
79 #endif
80 #if defined(I2C3_BASE)
81 [2] = { .pa = I2C3_BASE, },
82 #endif
83 #if defined(I2C4_BASE)
84 [3] = { .pa = I2C4_BASE, },
85 #endif
86 #if defined(I2C5_BASE)
87 [4] = { .pa = I2C5_BASE, },
88 #endif
89 #if defined(I2C6_BASE)
90 [5] = { .pa = I2C6_BASE, },
91 #endif
92
93 #endif
94 };
95 #endif
96
97 static struct imx_i2c_clk {
98 struct io_pa_va base;
99 uint32_t i2c[ARRAY_SIZE(i2c_bus)];
100 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)];
101 } i2c_clk = {
102 .base.pa = CCM_BASE,
103 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), I2C_CLK_CGR(4), },
104 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), I2C_CLK_CGR6BM(4),},
105 };
106
107 static struct imx_i2c_mux {
108 struct io_pa_va base;
109 struct imx_i2c_mux_regs {
110 uint32_t scl_mux;
111 uint32_t scl_cfg;
112 uint32_t scl_inp;
113 uint32_t sda_mux;
114 uint32_t sda_cfg;
115 uint32_t sda_inp;
116 } i2c[ARRAY_SIZE(i2c_bus)];
117 } i2c_mux = {
118 .base.pa = IOMUXC_BASE,
119 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1),
120 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1),
121 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), },
122 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2),
123 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2),
124 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), },
125 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3),
126 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3),
127 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), },
128 { .scl_mux = I2C_MUX_SCL(4), .scl_cfg = I2C_CFG_SCL(4),
129 .scl_inp = I2C_INP_SCL(4), .sda_mux = I2C_MUX_SDA(4),
130 .sda_cfg = I2C_CFG_SDA(4), .sda_inp = I2C_INP_SDA(4), },},
131 };
132
133 #define I2DR 0x10
134 #define I2SR 0x0C
135 #define I2CR 0x08
136 #define IFDR 0x04
137
138 #define I2CR_IEN BIT(7)
139 #define I2CR_IIEN BIT(6)
140 #define I2CR_MSTA BIT(5)
141 #define I2CR_MTX BIT(4)
142 #define I2CR_TX_NO_AK BIT(3)
143 #define I2CR_RSTA BIT(2)
144
145 #define I2SR_ICF BIT(7)
146 #define I2SR_IBB BIT(5)
147 #define I2SR_IAL BIT(4)
148 #define I2SR_IIF BIT(1)
149 #define I2SR_RX_NO_AK BIT(0)
150
i2c_io_read8(uint8_t bid,uint32_t address)151 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address)
152 {
153 return io_read8(i2c_bus[bid].va + address);
154 }
155
i2c_io_write8(uint8_t bid,uint32_t address,uint8_t data)156 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data)
157 {
158 return io_write8(i2c_bus[bid].va + address, data);
159 }
160
bus_is_idle(uint32_t sr)161 static bool bus_is_idle(uint32_t sr)
162 {
163 return (sr & I2SR_IBB) == 0;
164 }
165
bus_is_busy(uint32_t sr)166 static bool bus_is_busy(uint32_t sr)
167 {
168 return !bus_is_idle(sr);
169 }
170
isr_active(uint32_t sr)171 static bool isr_active(uint32_t sr)
172 {
173 return (sr & I2SR_IIF) == I2SR_IIF;
174 }
175
176 static struct ifdr_pair {
177 uint32_t divider;
178 uint8_t prescaler;
179 } ifdr_table[] = {
180 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
181 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
182 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
183 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
184 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
185 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
186 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
187 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
188 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
189 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
190 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
191 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
192 { 3072, 0x1E }, { 3840, 0x1F }
193 };
194
i2c_set_prescaler(uint8_t bid,uint32_t bps)195 static void i2c_set_prescaler(uint8_t bid, uint32_t bps)
196 {
197 struct ifdr_pair *p = ifdr_table;
198 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1;
199 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps;
200
201 if (div < p->divider)
202 q = p;
203 else if (div > q->divider)
204 p = q;
205
206 while (p != q) {
207 if (div <= p->divider)
208 break;
209 p++;
210 }
211
212 i2c_io_write8(bid, IFDR, p->prescaler);
213 }
214
i2c_set_bus_speed(uint8_t bid,int bps)215 static void i2c_set_bus_speed(uint8_t bid, int bps)
216 {
217 vaddr_t addr = i2c_clk.base.va;
218 uint32_t val = 0;
219
220 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MP) || \
221 defined(CFG_MX8MN)
222 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]);
223 val = CCM_CCGRx_ALWAYS_ON(0);
224 #elif defined(CFG_MX6ULL)
225 addr += i2c_clk.i2c[bid];
226 val = i2c_clk.cgrbm[bid] | io_read32(addr);
227 #else
228 #error IMX_I2C driver not supported on this platform
229 #endif
230 io_write32(addr, val);
231 i2c_set_prescaler(bid, bps);
232 }
233
i2c_sync_bus(uint8_t bid,bool (* match)(uint32_t),uint32_t * status)234 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t),
235 uint32_t *status)
236 {
237 uint64_t tref = timeout_init_us(100000);
238 uint32_t sr = 0;
239
240 while (!timeout_elapsed(tref)) {
241 sr = i2c_io_read8(bid, I2SR);
242 if (sr & I2SR_IAL) {
243 EMSG("bus arbitration lost");
244 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL);
245 return TEE_ERROR_COMMUNICATION;
246 }
247 if ((*match)(sr)) {
248 if (status)
249 *status = sr;
250 return TEE_SUCCESS;
251 }
252 }
253
254 return TEE_ERROR_BUSY;
255 }
256
i2c_idle_bus(uint8_t bid)257 static TEE_Result i2c_idle_bus(uint8_t bid)
258 {
259 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA;
260 TEE_Result ret = TEE_SUCCESS;
261
262 i2c_io_write8(bid, I2CR, tmp);
263 ret = i2c_sync_bus(bid, &bus_is_idle, NULL);
264 i2c_io_write8(bid, I2SR, 0);
265
266 return ret;
267 }
268
i2c_write_byte(uint8_t bid,uint8_t byte)269 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte)
270 {
271 TEE_Result ret = TEE_SUCCESS;
272 uint32_t status = 0;
273
274 i2c_io_write8(bid, I2DR, byte);
275 ret = i2c_sync_bus(bid, &isr_active, &status);
276 i2c_io_write8(bid, I2SR, 0);
277
278 if (!ret && (status & I2SR_RX_NO_AK))
279 return TEE_ERROR_BAD_STATE;
280
281 return ret;
282 }
283
i2c_read_byte(uint8_t bid,uint8_t * p)284 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p)
285 {
286 TEE_Result ret = TEE_SUCCESS;
287
288 *p = i2c_io_read8(bid, I2DR);
289 ret = i2c_sync_bus(bid, &isr_active, NULL);
290 i2c_io_write8(bid, I2SR, 0);
291
292 return ret;
293 }
294
i2c_write_data(uint8_t bid,const uint8_t * buf,int len)295 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len)
296 {
297 TEE_Result ret = TEE_SUCCESS;
298 uint32_t tmp = 0;
299
300 if (!len)
301 return TEE_SUCCESS;
302
303 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK;
304 i2c_io_write8(bid, I2CR, tmp);
305
306 while (len--) {
307 ret = i2c_write_byte(bid, *buf++);
308 if (ret)
309 return ret;
310 }
311
312 return ret;
313 }
314
i2c_read_data(uint8_t bid,uint8_t * buf,int len)315 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len)
316 {
317 TEE_Result ret = TEE_SUCCESS;
318 uint8_t dummy = 0;
319 uint32_t tmp = 0;
320
321 if (!len)
322 return TEE_SUCCESS;
323
324 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX;
325 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK;
326 i2c_io_write8(bid, I2CR, tmp);
327 i2c_io_read8(bid, I2DR);
328
329 ret = i2c_read_byte(bid, &dummy);
330 if (ret)
331 return ret;
332
333 /*
334 * A data transfer ends when the master signals a stop; for a master
335 * receiver to terminate a transfer it must inform the slave transmiter
336 * by not acknowledging the last data byte. This is done by setting the
337 * transmit acknowledge bit before reading the next-to-last byte.
338 */
339 do {
340 if (len == 2) {
341 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK;
342 i2c_io_write8(bid, I2CR, tmp);
343 }
344
345 ret = i2c_read_byte(bid, buf++);
346 if (ret)
347 return ret;
348 } while (len--);
349
350 return ret;
351 }
352
i2c_init_transfer(uint8_t bid,uint8_t chip)353 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip)
354 {
355 TEE_Result ret = TEE_SUCCESS;
356 uint32_t tmp = 0;
357
358 ret = i2c_idle_bus(bid);
359 if (ret)
360 return ret;
361
362 /* Enable the interface */
363 tmp = !(i2c_io_read8(bid, I2CR) & I2CR_IEN);
364 if (tmp) {
365 i2c_io_write8(bid, I2CR, I2CR_IEN);
366 udelay(50);
367 }
368 i2c_io_write8(bid, I2SR, 0);
369
370 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA;
371 i2c_io_write8(bid, I2CR, tmp);
372
373 /* Wait until the bus is active */
374 ret = i2c_sync_bus(bid, &bus_is_busy, NULL);
375 if (ret)
376 return ret;
377
378 /* Slave address on the bus */
379 return i2c_write_data(bid, &chip, 1);
380 }
381
imx_i2c_read(uint8_t bid,uint8_t chip,uint8_t * buf,int len)382 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len)
383 {
384 TEE_Result ret = TEE_SUCCESS;
385
386 if (bid >= ARRAY_SIZE(i2c_bus))
387 return TEE_ERROR_BAD_PARAMETERS;
388
389 if ((len && !buf) || chip > 0x7F)
390 return TEE_ERROR_BAD_PARAMETERS;
391
392 if (!i2c_bus[bid].va)
393 return TEE_ERROR_BAD_PARAMETERS;
394
395 ret = i2c_init_transfer(bid, chip << 1 | BIT(0));
396 if (!ret)
397 ret = i2c_read_data(bid, buf, len);
398
399 if (i2c_idle_bus(bid))
400 IMSG("bus not idle");
401
402 return ret;
403 }
404
imx_i2c_write(uint8_t bid,uint8_t chip,const uint8_t * buf,int len)405 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len)
406 {
407 TEE_Result ret = TEE_SUCCESS;
408
409 if (bid >= ARRAY_SIZE(i2c_bus))
410 return TEE_ERROR_BAD_PARAMETERS;
411
412 if ((len && !buf) || chip > 0x7F)
413 return TEE_ERROR_BAD_PARAMETERS;
414
415 if (!i2c_bus[bid].va)
416 return TEE_ERROR_BAD_PARAMETERS;
417
418 ret = i2c_init_transfer(bid, chip << 1);
419 if (!ret)
420 ret = i2c_write_data(bid, buf, len);
421
422 if (i2c_idle_bus(bid))
423 IMSG("bus not idle");
424
425 return ret;
426 }
427
imx_i2c_probe(uint8_t bid,uint8_t chip)428 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip)
429 {
430 if (bid >= ARRAY_SIZE(i2c_bus))
431 return TEE_ERROR_BAD_PARAMETERS;
432
433 if (!i2c_bus[bid].va)
434 return TEE_ERROR_BAD_PARAMETERS;
435
436 if (chip > 0x7F)
437 return TEE_ERROR_BAD_PARAMETERS;
438
439 return imx_i2c_write(bid, chip, NULL, 0);
440 }
441
442 /*
443 * I2C bus initialization: configure the IOMUX and enable the clock.
444 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3), (3=I2C4).
445 * @bps: Bus baud rate, in bits per second.
446 */
imx_i2c_init(uint8_t bid,int bps)447 TEE_Result imx_i2c_init(uint8_t bid, int bps)
448 {
449 struct imx_i2c_mux *mux = &i2c_mux;
450
451 if (bid >= ARRAY_SIZE(i2c_bus))
452 return TEE_ERROR_BAD_PARAMETERS;
453
454 if (!bps)
455 return TEE_ERROR_BAD_PARAMETERS;
456
457 if (!i2c_bus[bid].va)
458 return TEE_ERROR_BAD_PARAMETERS;
459
460 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid));
461 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid));
462 if (mux->i2c[bid].scl_inp)
463 io_write32(mux->base.va + mux->i2c[bid].scl_inp,
464 I2C_INP_VAL(bid + 1));
465
466 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid));
467 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid));
468 if (mux->i2c[bid].sda_inp)
469 io_write32(mux->base.va + mux->i2c[bid].sda_inp,
470 I2C_INP_VAL(bid + 2));
471
472 /* Baud rate in bits per second */
473 i2c_set_bus_speed(bid, bps);
474
475 return TEE_SUCCESS;
476 }
477
get_va(paddr_t pa,vaddr_t * va)478 static TEE_Result get_va(paddr_t pa, vaddr_t *va)
479 {
480 *va = (vaddr_t)core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000);
481 if (!*va)
482 return TEE_ERROR_GENERIC;
483
484 return TEE_SUCCESS;
485 }
486
487 #if defined(CFG_DT) && !defined(CFG_EXTERNAL_DTB_OVERLAY)
488 static const char *const dt_i2c_match_table[] = {
489 "fsl,imx21-i2c",
490 };
491
i2c_mapped(const char * i2c_match)492 static TEE_Result i2c_mapped(const char *i2c_match)
493 {
494 TEE_Result ret = TEE_ERROR_GENERIC;
495 void *fdt = get_dt();
496 size_t size = 0;
497 size_t i = 0;
498 int off = 0;
499
500 if (!fdt)
501 return TEE_ERROR_NOT_SUPPORTED;
502
503 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
504 off = fdt_node_offset_by_compatible(fdt, off, i2c_match);
505 if (off < 0)
506 break;
507
508 if (!(_fdt_get_status(fdt, off) & DT_STATUS_OK_SEC)) {
509 EMSG("i2c%zu not enabled", i + 1);
510 continue;
511 }
512
513 if (dt_map_dev(fdt, off, &i2c_bus[i].va, &size,
514 DT_MAP_AUTO) < 0) {
515 EMSG("i2c%zu not enabled", i + 1);
516 continue;
517 }
518
519 i2c_bus[i].pa = virt_to_phys((void *)i2c_bus[i].va);
520 ret = TEE_SUCCESS;
521 }
522
523 return ret;
524 }
525
i2c_map_controller(void)526 static TEE_Result i2c_map_controller(void)
527 {
528 TEE_Result ret = TEE_ERROR_GENERIC;
529 size_t i = 0;
530
531 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) {
532 ret = i2c_mapped(dt_i2c_match_table[i]);
533 if (!ret || ret == TEE_ERROR_NOT_SUPPORTED)
534 return ret;
535 }
536
537 return ret;
538 }
539 #else
i2c_map_controller(void)540 static TEE_Result i2c_map_controller(void)
541 {
542 TEE_Result ret = TEE_ERROR_GENERIC;
543 size_t n = 0;
544
545 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) {
546 if (i2c_bus[n].pa) {
547 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va))
548 EMSG("i2c%zu not enabled", n + 1);
549 else
550 ret = TEE_SUCCESS;
551 } else {
552 IMSG("i2c%zu not enabled", n + 1);
553 }
554 }
555
556 return ret;
557 }
558 #endif
559
i2c_init(void)560 static TEE_Result i2c_init(void)
561 {
562 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va))
563 return TEE_ERROR_GENERIC;
564
565 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va))
566 return TEE_ERROR_GENERIC;
567
568 return i2c_map_controller();
569 }
570
571 early_init(i2c_init);
572