1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2021, STMicroelectronics
4 *
5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs.
6 * The driver API is defined in header file stm32_gpio.h.
7 */
8
9 #include <assert.h>
10 #include <drivers/clk.h>
11 #include <drivers/clk_dt.h>
12 #include <drivers/stm32_gpio.h>
13 #include <io.h>
14 #include <kernel/dt.h>
15 #include <kernel/boot.h>
16 #include <kernel/panic.h>
17 #include <kernel/spinlock.h>
18 #include <libfdt.h>
19 #include <mm/core_memprot.h>
20 #include <stdbool.h>
21 #include <stm32_util.h>
22 #include <trace.h>
23 #include <util.h>
24
25 #define GPIO_PIN_MAX 15
26
27 #define GPIO_MODER_OFFSET 0x00
28 #define GPIO_OTYPER_OFFSET 0x04
29 #define GPIO_OSPEEDR_OFFSET 0x08
30 #define GPIO_PUPDR_OFFSET 0x0c
31 #define GPIO_IDR_OFFSET 0x10
32 #define GPIO_ODR_OFFSET 0x14
33 #define GPIO_BSRR_OFFSET 0x18
34 #define GPIO_AFRL_OFFSET 0x20
35 #define GPIO_AFRH_OFFSET 0x24
36 #define GPIO_SECR_OFFSET 0x30
37
38 #define GPIO_ALT_LOWER_LIMIT 0x8
39
40 #define GPIO_MODE_MASK GENMASK_32(1, 0)
41 #define GPIO_OSPEED_MASK GENMASK_32(1, 0)
42 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0)
43 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0)
44
45 #define DT_GPIO_BANK_SHIFT 12
46 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12)
47 #define DT_GPIO_PIN_SHIFT 8
48 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8)
49 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0)
50
51 static unsigned int gpio_lock;
52
53 /* Save to output @cfg the current GPIO (@bank/@pin) configuration */
get_gpio_cfg(uint32_t bank,uint32_t pin,struct gpio_cfg * cfg)54 static void get_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg)
55 {
56 vaddr_t base = stm32_get_gpio_bank_base(bank);
57 struct clk *clk = stm32_get_gpio_bank_clk(bank);
58
59 clk_enable(clk);
60
61 /*
62 * Save GPIO configuration bits spread over the few bank registers.
63 * 1bit fields are accessed at bit position being the pin index.
64 * 2bit fields are accessed at bit position being twice the pin index.
65 * 4bit fields are accessed at bit position being fourth the pin index
66 * but accessed from 2 32bit registers at incremental addresses.
67 */
68 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
69 GPIO_MODE_MASK;
70
71 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1;
72
73 cfg->ospeed = (io_read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) &
74 GPIO_OSPEED_MASK;
75
76 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) &
77 GPIO_PUPD_PULL_MASK;
78
79 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;
80
81 if (pin < GPIO_ALT_LOWER_LIMIT)
82 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) &
83 GPIO_ALTERNATE_MASK;
84 else
85 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >>
86 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) &
87 GPIO_ALTERNATE_MASK;
88
89 clk_disable(clk);
90 }
91
92 /* Apply GPIO (@bank/@pin) configuration described by @cfg */
set_gpio_cfg(uint32_t bank,uint32_t pin,struct gpio_cfg * cfg)93 static void set_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg)
94 {
95 vaddr_t base = stm32_get_gpio_bank_base(bank);
96 struct clk *clk = stm32_get_gpio_bank_clk(bank);
97 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock);
98
99 clk_enable(clk);
100
101 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */
102 io_clrsetbits32(base + GPIO_MODER_OFFSET,
103 GPIO_MODE_MASK << (pin << 1),
104 cfg->mode << (pin << 1));
105
106 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */
107 io_clrsetbits32(base + GPIO_OTYPER_OFFSET, BIT(pin), cfg->otype << pin);
108
109 /* Load GPIO Output Speed confguration, 2bit value */
110 io_clrsetbits32(base + GPIO_OSPEEDR_OFFSET,
111 GPIO_OSPEED_MASK << (pin << 1),
112 cfg->ospeed << (pin << 1));
113
114 /* Load GPIO pull configuration, 2bit value */
115 io_clrsetbits32(base + GPIO_PUPDR_OFFSET, BIT(pin),
116 cfg->pupd << (pin << 1));
117
118 /* Load pin mux Alternate Function configuration, 4bit value */
119 if (pin < GPIO_ALT_LOWER_LIMIT) {
120 io_clrsetbits32(base + GPIO_AFRL_OFFSET,
121 GPIO_ALTERNATE_MASK << (pin << 2),
122 cfg->af << (pin << 2));
123 } else {
124 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;
125
126 io_clrsetbits32(base + GPIO_AFRH_OFFSET,
127 GPIO_ALTERNATE_MASK << shift,
128 cfg->af << shift);
129 }
130
131 /* Load GPIO Output direction confuguration, 1bit */
132 io_clrsetbits32(base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin);
133
134 clk_disable(clk);
135 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
136 }
137
stm32_pinctrl_load_active_cfg(struct stm32_pinctrl * pinctrl,size_t cnt)138 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt)
139 {
140 size_t n = 0;
141
142 for (n = 0; n < cnt; n++)
143 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin,
144 &pinctrl[n].active_cfg);
145 }
146
stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl * pinctrl,size_t cnt)147 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt)
148 {
149 size_t n = 0;
150
151 for (n = 0; n < cnt; n++)
152 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin,
153 &pinctrl[n].standby_cfg);
154 }
155
stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl * pinctrl,size_t cnt)156 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt)
157 {
158 size_t n = 0;
159
160 for (n = 0; n < cnt; n++)
161 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin,
162 &pinctrl[n].standby_cfg);
163 }
164
165 #ifdef CFG_DT
166 /* Panic if GPIO bank information from platform do not match DTB description */
ckeck_gpio_bank(void * fdt,uint32_t bank,int pinctrl_node)167 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node)
168 {
169 int pinctrl_subnode = 0;
170
171 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) {
172 TEE_Result res = TEE_ERROR_GENERIC;
173 const fdt32_t *cuint = NULL;
174 struct clk *clk = NULL;
175
176 if (fdt_getprop(fdt, pinctrl_subnode,
177 "gpio-controller", NULL) == NULL)
178 continue;
179
180 /* Check bank register offset matches platform assumptions */
181 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL);
182 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank))
183 continue;
184
185 /* Check bank clock matches platform assumptions */
186 res = clk_dt_get_by_index(fdt, pinctrl_subnode, 0, &clk);
187 if (res || clk != stm32_get_gpio_bank_clk(bank))
188 panic();
189
190 /* Check controller is enabled */
191 if (_fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED)
192 panic();
193
194 return;
195 }
196
197 panic();
198 }
199
200 /* Count pins described in the DT node and get related data if possible */
get_pinctrl_from_fdt(void * fdt,int node,struct stm32_pinctrl * pinctrl,size_t count)201 static int get_pinctrl_from_fdt(void *fdt, int node,
202 struct stm32_pinctrl *pinctrl, size_t count)
203 {
204 const fdt32_t *cuint, *slewrate;
205 int len = 0;
206 int pinctrl_node = 0;
207 uint32_t i = 0;
208 uint32_t speed = GPIO_OSPEED_LOW;
209 uint32_t pull = GPIO_PUPD_NO_PULL;
210 size_t found = 0;
211
212 cuint = fdt_getprop(fdt, node, "pinmux", &len);
213 if (!cuint)
214 return -FDT_ERR_NOTFOUND;
215
216 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node));
217 if (pinctrl_node < 0)
218 return -FDT_ERR_NOTFOUND;
219
220 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL);
221 if (slewrate)
222 speed = fdt32_to_cpu(*slewrate);
223
224 if (fdt_getprop(fdt, node, "bias-pull-up", NULL))
225 pull = GPIO_PUPD_PULL_UP;
226 if (fdt_getprop(fdt, node, "bias-pull-down", NULL))
227 pull = GPIO_PUPD_PULL_DOWN;
228
229 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
230 uint32_t pincfg = 0;
231 uint32_t bank = 0;
232 uint32_t pin = 0;
233 uint32_t mode = 0;
234 uint32_t alternate = 0;
235 bool opendrain = false;
236
237 pincfg = fdt32_to_cpu(*cuint);
238 cuint++;
239
240 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;
241
242 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;
243
244 mode = pincfg & DT_GPIO_MODE_MASK;
245
246 switch (mode) {
247 case 0:
248 mode = GPIO_MODE_INPUT;
249 break;
250 case 1:
251 case 2:
252 case 3:
253 case 4:
254 case 5:
255 case 6:
256 case 7:
257 case 8:
258 case 9:
259 case 10:
260 case 11:
261 case 12:
262 case 13:
263 case 14:
264 case 15:
265 case 16:
266 alternate = mode - 1U;
267 mode = GPIO_MODE_ALTERNATE;
268 break;
269 case 17:
270 mode = GPIO_MODE_ANALOG;
271 break;
272 default:
273 mode = GPIO_MODE_OUTPUT;
274 break;
275 }
276
277 if (fdt_getprop(fdt, node, "drive-open-drain", NULL))
278 opendrain = true;
279
280 /* Check GPIO bank clock/base address against platform */
281 ckeck_gpio_bank(fdt, bank, pinctrl_node);
282
283 if (found < count) {
284 struct stm32_pinctrl *ref = &pinctrl[found];
285
286 ref->bank = (uint8_t)bank;
287 ref->pin = (uint8_t)pin;
288 ref->active_cfg.mode = mode;
289 ref->active_cfg.otype = opendrain ? 1 : 0;
290 ref->active_cfg.ospeed = speed;
291 ref->active_cfg.pupd = pull;
292 ref->active_cfg.od = 0;
293 ref->active_cfg.af = alternate;
294 /* Default to analog mode for standby state */
295 ref->standby_cfg.mode = GPIO_MODE_ANALOG;
296 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL;
297 }
298
299 found++;
300 }
301
302 return (int)found;
303 }
304
stm32_pinctrl_fdt_get_pinctrl(void * fdt,int device_node,struct stm32_pinctrl * pinctrl,size_t count)305 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node,
306 struct stm32_pinctrl *pinctrl, size_t count)
307 {
308 const fdt32_t *cuint = NULL;
309 int lenp = 0;
310 int i = 0;
311 size_t found = 0;
312
313 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp);
314 if (!cuint)
315 return -FDT_ERR_NOTFOUND;
316
317 for (i = 0; i < (lenp / 4); i++) {
318 int node = 0;
319 int subnode = 0;
320
321 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
322 if (node < 0)
323 return -FDT_ERR_NOTFOUND;
324
325 fdt_for_each_subnode(subnode, fdt, node) {
326 size_t n = 0;
327 int rc = 0;
328
329 if (count > found)
330 n = count - found;
331 else
332 n = 0;
333
334 rc = get_pinctrl_from_fdt(fdt, subnode,
335 &pinctrl[found], n);
336 if (rc < 0)
337 return rc;
338
339 found += (size_t)rc;
340 }
341
342 cuint++;
343 }
344
345 return (int)found;
346 }
347
stm32_get_gpio_count(void * fdt,int pinctrl_node,unsigned int bank)348 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank)
349 {
350 int node = 0;
351 const fdt32_t *cuint = NULL;
352
353 fdt_for_each_subnode(node, fdt, pinctrl_node) {
354 if (!fdt_getprop(fdt, node, "gpio-controller", NULL))
355 continue;
356
357 cuint = fdt_getprop(fdt, node, "reg", NULL);
358 if (!cuint)
359 continue;
360
361 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank))
362 continue;
363
364 cuint = fdt_getprop(fdt, node, "ngpios", NULL);
365 if (!cuint)
366 panic();
367
368 return (int)fdt32_to_cpu(*cuint);
369 }
370
371 return -1;
372 }
373 #endif /*CFG_DT*/
374
valid_gpio_config(unsigned int bank,unsigned int pin,bool input)375 static __maybe_unused bool valid_gpio_config(unsigned int bank,
376 unsigned int pin, bool input)
377 {
378 vaddr_t base = stm32_get_gpio_bank_base(bank);
379 uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) &
380 GPIO_MODE_MASK;
381
382 if (pin > GPIO_PIN_MAX)
383 return false;
384
385 if (input)
386 return mode == GPIO_MODE_INPUT;
387 else
388 return mode == GPIO_MODE_OUTPUT;
389 }
390
stm32_gpio_get_input_level(unsigned int bank,unsigned int pin)391 int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin)
392 {
393 vaddr_t base = stm32_get_gpio_bank_base(bank);
394 struct clk *clk = stm32_get_gpio_bank_clk(bank);
395 int rc = 0;
396
397 clk_enable(clk);
398
399 assert(valid_gpio_config(bank, pin, true));
400
401 if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin))
402 rc = 1;
403
404 clk_disable(clk);
405
406 return rc;
407 }
408
stm32_gpio_set_output_level(unsigned int bank,unsigned int pin,int level)409 void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int level)
410 {
411 vaddr_t base = stm32_get_gpio_bank_base(bank);
412 struct clk *clk = stm32_get_gpio_bank_clk(bank);
413
414 clk_enable(clk);
415
416 assert(valid_gpio_config(bank, pin, false));
417
418 if (level)
419 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin));
420 else
421 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin + 16));
422
423 clk_disable(clk);
424 }
425
stm32_gpio_set_secure_cfg(unsigned int bank,unsigned int pin,bool secure)426 void stm32_gpio_set_secure_cfg(unsigned int bank, unsigned int pin, bool secure)
427 {
428 vaddr_t base = stm32_get_gpio_bank_base(bank);
429 struct clk *clk = stm32_get_gpio_bank_clk(bank);
430 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock);
431
432 clk_enable(clk);
433
434 if (secure)
435 io_setbits32(base + GPIO_SECR_OFFSET, BIT(pin));
436 else
437 io_clrbits32(base + GPIO_SECR_OFFSET, BIT(pin));
438
439 clk_disable(clk);
440 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
441 }
442