1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021-2022, STMicroelectronics
4 */
5
6 #include <drivers/clk.h>
7 #include <drivers/clk_dt.h>
8 #include <drivers/stm32_tamp.h>
9 #include <io.h>
10 #include <kernel/dt.h>
11 #include <kernel/interrupt.h>
12 #include <libfdt.h>
13 #include <mm/core_memprot.h>
14 #include <stdbool.h>
15
16 /* STM32 Registers */
17 #define _TAMP_CR1 0x00U
18 #define _TAMP_CR2 0x04U
19 #define _TAMP_CR3 0x08U
20 #define _TAMP_FLTCR 0x0CU
21 #define _TAMP_ATCR1 0x10U
22 #define _TAMP_ATSEEDR 0x14U
23 #define _TAMP_ATOR 0x18U
24 #define _TAMP_ATCR2 0x1CU
25 #define _TAMP_SECCFGR 0x20U
26 #define _TAMP_SMCR 0x20U
27 #define _TAMP_PRIVCFGR 0x24U
28 #define _TAMP_IER 0x2CU
29 #define _TAMP_SR 0x30U
30 #define _TAMP_MISR 0x34U
31 #define _TAMP_SMISR 0x38U
32 #define _TAMP_SCR 0x3CU
33 #define _TAMP_COUNTR 0x40U
34 #define _TAMP_COUNT2R 0x44U
35 #define _TAMP_OR 0x50U
36 #define _TAMP_ERCFGR 0X54U
37 #define _TAMP_HWCFGR2 0x3ECU
38 #define _TAMP_HWCFGR1 0x3F0U
39 #define _TAMP_VERR 0x3F4U
40 #define _TAMP_IPIDR 0x3F8U
41 #define _TAMP_SIDR 0x3FCU
42
43 /* _TAMP_SECCFGR bit fields */
44 #define _TAMP_SECCFGR_BKPRWSEC_MASK GENMASK_32(7, 0)
45 #define _TAMP_SECCFGR_BKPRWSEC_SHIFT 0U
46 #define _TAMP_SECCFGR_CNT2SEC BIT(14)
47 #define _TAMP_SECCFGR_CNT1SEC BIT(15)
48 #define _TAMP_SECCFGR_BKPWSEC_MASK GENMASK_32(23, 16)
49 #define _TAMP_SECCFGR_BKPWSEC_SHIFT 16U
50 #define _TAMP_SECCFGR_BHKLOCK BIT(30)
51 #define _TAMP_SECCFGR_TAMPSEC BIT(31)
52 #define _TAMP_SECCFGR_BUT_BKP_MASK (GENMASK_32(31, 30) | \
53 GENMASK_32(15, 14))
54
55 /* _TAMP_SMCR bit fields */
56 #define _TAMP_SMCR_BKPRWDPROT_MASK GENMASK_32(7, 0)
57 #define _TAMP_SMCR_BKPRWDPROT_SHIFT 0U
58 #define _TAMP_SMCR_BKPWDPROT_MASK GENMASK_32(23, 16)
59 #define _TAMP_SMCR_BKPWDPROT_SHIFT 16U
60 #define _TAMP_SMCR_DPROT BIT(31)
61 /*
62 * _TAMP_PRIVCFGR bit fields
63 */
64 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14)
65 #define _TAMP_PRIVCFG_CNT1PRIV BIT(15)
66 #define _TAMP_PRIVCFG_BKPRWPRIV BIT(29)
67 #define _TAMP_PRIVCFG_BKPWPRIV BIT(30)
68 #define _TAMP_PRIVCFG_TAMPPRIV BIT(31)
69 #define _TAMP_PRIVCFGR_MASK (GENMASK_32(31, 29) | \
70 GENMASK_32(15, 14))
71
72 /*
73 * _TAMP_PRIVCFGR bit fields
74 */
75 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14)
76 #define _TAMP_PRIVCFG_CNT1PRIV BIT(15)
77 #define _TAMP_PRIVCFG_BKPRWPRIV BIT(29)
78 #define _TAMP_PRIVCFG_BKPWPRIV BIT(30)
79 #define _TAMP_PRIVCFG_TAMPPRIV BIT(31)
80 #define _TAMP_PRIVCFGR_MASK (GENMASK_32(31, 29) | \
81 GENMASK_32(15, 14))
82
83 /* _TAMP_HWCFGR2 bit fields */
84 #define _TAMP_HWCFGR2_TZ GENMASK_32(11, 8)
85 #define _TAMP_HWCFGR2_OR GENMASK_32(7, 0)
86
87 /* _TAMP_HWCFGR1 bit fields */
88 #define _TAMP_HWCFGR1_BKPREG GENMASK_32(7, 0)
89 #define _TAMP_HWCFGR1_TAMPER GENMASK_32(11, 8)
90 #define _TAMP_HWCFGR1_ACTIVE GENMASK_32(15, 12)
91 #define _TAMP_HWCFGR1_INTERN GENMASK_32(31, 16)
92 #define _TAMP_HWCFGR1_ITAMP_MAX_ID 16U
93 #define _TAMP_HWCFGR1_ITAMP(id) BIT((id) - INT_TAMP1 + 16U)
94
95 /* _TAMP_VERR bit fields */
96 #define _TAMP_VERR_MINREV GENMASK_32(3, 0)
97 #define _TAMP_VERR_MAJREV GENMASK_32(7, 4)
98
99 /*
100 * TAMP instance data
101 * @base - IOMEM base address
102 * @clock - TAMP clock
103 * @it - TAMP interrupt number
104 * @hwconf1 - Copy of TAMP HWCONF1 register content
105 * @hwconf2 - Copy of TAMP HWCONF2 register content
106 * @compat - Reference to compat data passed at driver initialization
107 */
108 struct stm32_tamp_instance {
109 struct io_pa_va base;
110 struct clk *clock;
111 int it;
112 uint32_t hwconf1;
113 uint32_t hwconf2;
114 struct stm32_tamp_compat *compat;
115 };
116
117 /*
118 * Compatibility capabilities
119 * TAMP_HAS_REGISTER_SECCFG - Supports SECCFGR, otherwise supports SMCR register
120 * TAMP_HAS_REGISTER_PRIVCFG - Supports PRIVCFGR configuration register
121 */
122 #define TAMP_HAS_REGISTER_SECCFG BIT(0)
123 #define TAMP_HAS_REGISTER_PRIVCFGR BIT(1)
124
125 /*
126 * @nb_monotonic_counter - Number of monotic counter supported
127 * @tags - Bit flags TAMP_HAS_* for compatibily management
128 */
129 struct stm32_tamp_compat {
130 int nb_monotonic_counter;
131 uint32_t tags;
132 };
133
134 /* Expects at most a single instance */
135 static struct stm32_tamp_instance *stm32_tamp_device;
136
stm32_tamp_set_secure_bkpregs(struct stm32_bkpregs_conf * bkr_conf)137 TEE_Result stm32_tamp_set_secure_bkpregs(struct stm32_bkpregs_conf *bkr_conf)
138 {
139 struct stm32_tamp_instance *tamp = stm32_tamp_device;
140 vaddr_t base = 0;
141 uint32_t first_z2 = 0;
142 uint32_t first_z3 = 0;
143
144 if (!tamp)
145 return TEE_ERROR_DEFER_DRIVER_INIT;
146
147 if (!bkr_conf)
148 return TEE_ERROR_BAD_PARAMETERS;
149
150 base = io_pa_or_va(&tamp->base, 1);
151
152 first_z2 = bkr_conf->nb_zone1_regs;
153 first_z3 = bkr_conf->nb_zone1_regs + bkr_conf->nb_zone2_regs;
154
155 if ((first_z2 > (tamp->hwconf1 & _TAMP_HWCFGR1_BKPREG)) ||
156 (first_z3 > (tamp->hwconf1 & _TAMP_HWCFGR1_BKPREG)))
157 return TEE_ERROR_BAD_PARAMETERS;
158
159 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_SECCFG)) {
160 io_clrsetbits32(base + _TAMP_SECCFGR,
161 _TAMP_SECCFGR_BKPRWSEC_MASK,
162 (first_z2 << _TAMP_SECCFGR_BKPRWSEC_SHIFT) &
163 _TAMP_SECCFGR_BKPRWSEC_MASK);
164
165 io_clrsetbits32(base + _TAMP_SECCFGR,
166 _TAMP_SECCFGR_BKPWSEC_MASK,
167 (first_z3 << _TAMP_SECCFGR_BKPWSEC_SHIFT) &
168 _TAMP_SECCFGR_BKPWSEC_MASK);
169 } else {
170 io_clrsetbits32(base + _TAMP_SMCR,
171 _TAMP_SMCR_BKPRWDPROT_MASK,
172 (first_z2 << _TAMP_SMCR_BKPRWDPROT_SHIFT) &
173 _TAMP_SMCR_BKPRWDPROT_MASK);
174
175 io_clrsetbits32(base + _TAMP_SMCR,
176 _TAMP_SMCR_BKPWDPROT_MASK,
177 (first_z3 << _TAMP_SMCR_BKPWDPROT_SHIFT) &
178 _TAMP_SMCR_BKPWDPROT_MASK);
179 }
180
181 return TEE_SUCCESS;
182 }
183
stm32_tamp_set_secure(struct stm32_tamp_instance * tamp,uint32_t mode)184 static void stm32_tamp_set_secure(struct stm32_tamp_instance *tamp,
185 uint32_t mode)
186 {
187 vaddr_t base = io_pa_or_va(&tamp->base, 1);
188
189 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_SECCFG)) {
190 io_clrsetbits32(base + _TAMP_SECCFGR,
191 _TAMP_SECCFGR_BUT_BKP_MASK,
192 mode & _TAMP_SECCFGR_BUT_BKP_MASK);
193 } else {
194 /*
195 * Note: MP15 doesn't use SECCFG register and
196 * inverts the secure bit.
197 */
198 if (mode & _TAMP_SECCFGR_TAMPSEC)
199 io_clrbits32(base + _TAMP_SMCR, _TAMP_SMCR_DPROT);
200 else
201 io_setbits32(base + _TAMP_SMCR, _TAMP_SMCR_DPROT);
202 }
203 }
204
stm32_tamp_set_privilege(struct stm32_tamp_instance * tamp,uint32_t mode)205 static void stm32_tamp_set_privilege(struct stm32_tamp_instance *tamp,
206 uint32_t mode)
207 {
208 vaddr_t base = io_pa_or_va(&tamp->base, 1);
209
210 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_PRIVCFGR))
211 io_clrsetbits32(base + _TAMP_PRIVCFGR, _TAMP_PRIVCFGR_MASK,
212 mode & _TAMP_PRIVCFGR_MASK);
213 }
214
stm32_tamp_parse_fdt(struct stm32_tamp_instance * tamp,const void * fdt,int node,const void * compat)215 static TEE_Result stm32_tamp_parse_fdt(struct stm32_tamp_instance *tamp,
216 const void *fdt, int node,
217 const void *compat)
218 {
219 struct dt_node_info dt_tamp = { };
220
221 _fdt_fill_device_info(fdt, &dt_tamp, node);
222
223 if (dt_tamp.reg == DT_INFO_INVALID_REG ||
224 dt_tamp.reg_size == DT_INFO_INVALID_REG_SIZE)
225 return TEE_ERROR_BAD_PARAMETERS;
226
227 tamp->compat = (struct stm32_tamp_compat *)compat;
228 tamp->it = dt_tamp.interrupt;
229 tamp->base.pa = dt_tamp.reg;
230 io_pa_or_va_secure(&tamp->base, dt_tamp.reg_size);
231
232 return clk_dt_get_by_index(fdt, node, 0, &tamp->clock);
233 }
234
stm32_tamp_probe(const void * fdt,int node,const void * compat_data)235 static TEE_Result stm32_tamp_probe(const void *fdt, int node,
236 const void *compat_data)
237 {
238 struct stm32_tamp_instance *tamp = NULL;
239 uint32_t __maybe_unused revision = 0;
240 TEE_Result res = TEE_SUCCESS;
241 vaddr_t base = 0;
242
243 tamp = calloc(1, sizeof(*tamp));
244 if (!tamp)
245 return TEE_ERROR_OUT_OF_MEMORY;
246
247 res = stm32_tamp_parse_fdt(tamp, fdt, node, compat_data);
248 if (res)
249 goto err;
250
251 clk_enable(tamp->clock);
252
253 base = io_pa_or_va(&tamp->base, 1);
254
255 tamp->hwconf1 = io_read32(base + _TAMP_HWCFGR1);
256 tamp->hwconf2 = io_read32(base + _TAMP_HWCFGR2);
257
258 revision = io_read32(base + _TAMP_VERR);
259 FMSG("STM32 TAMPER V%"PRIx32".%"PRIu32,
260 (revision & _TAMP_VERR_MAJREV) >> 4, revision & _TAMP_VERR_MINREV);
261
262 if (!(tamp->hwconf2 & _TAMP_HWCFGR2_TZ)) {
263 EMSG("TAMP doesn't support TrustZone");
264 res = TEE_ERROR_NOT_SUPPORTED;
265 goto err_clk;
266 }
267
268 /*
269 * Enforce secure only access to protected TAMP registers.
270 * Allow non-secure access to monotonic counter.
271 */
272 stm32_tamp_set_secure(tamp, _TAMP_SECCFGR_TAMPSEC);
273
274 /*
275 * Enforce privilege only access to TAMP registers, backup
276 * registers and monotonic counter.
277 */
278 stm32_tamp_set_privilege(tamp, _TAMP_PRIVCFG_TAMPPRIV |
279 _TAMP_PRIVCFG_BKPRWPRIV |
280 _TAMP_PRIVCFG_BKPWPRIV);
281
282 stm32_tamp_device = tamp;
283
284 return TEE_SUCCESS;
285
286 err_clk:
287 clk_disable(tamp->clock);
288 err:
289 free(tamp);
290 return res;
291 }
292
293 static const struct stm32_tamp_compat mp13_compat = {
294 .nb_monotonic_counter = 2,
295 .tags = TAMP_HAS_REGISTER_SECCFG | TAMP_HAS_REGISTER_PRIVCFGR,
296 };
297
298 static const struct stm32_tamp_compat mp15_compat = {
299 .nb_monotonic_counter = 1,
300 .tags = 0,
301 };
302
303 static const struct dt_device_match stm32_tamp_match_table[] = {
304 { .compatible = "st,stm32mp13-tamp", .compat_data = &mp13_compat },
305 { .compatible = "st,stm32-tamp", .compat_data = &mp15_compat },
306 { }
307 };
308
309 DEFINE_DT_DRIVER(stm32_tamp_dt_driver) = {
310 .name = "stm32-tamp",
311 .match_table = stm32_tamp_match_table,
312 .probe = stm32_tamp_probe,
313 };
314