1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2017-2018, STMicroelectronics
4 */
5
6 #include <compiler.h>
7 #include <console.h>
8 #include <drivers/clk.h>
9 #include <drivers/clk_dt.h>
10 #include <drivers/serial.h>
11 #include <drivers/stm32_uart.h>
12 #include <io.h>
13 #include <keep.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/panic.h>
17 #include <libfdt.h>
18 #include <stm32_util.h>
19 #include <util.h>
20
21 #define UART_REG_CR1 0x00 /* Control register 1 */
22 #define UART_REG_CR2 0x04 /* Control register 2 */
23 #define UART_REG_CR3 0x08 /* Control register 3 */
24 #define UART_REG_BRR 0x0c /* Baud rate register */
25 #define UART_REG_RQR 0x18 /* Request register */
26 #define UART_REG_ISR 0x1c /* Interrupt & status reg. */
27 #define UART_REG_ICR 0x20 /* Interrupt flag clear reg. */
28 #define UART_REG_RDR 0x24 /* Receive data register */
29 #define UART_REG_TDR 0x28 /* Transmit data register */
30 #define UART_REG_PRESC 0x2c /* Prescaler register */
31
32 #define PUTC_TIMEOUT_US 1000
33 #define FLUSH_TIMEOUT_US 16000
34
35 /*
36 * Uart Interrupt & status register bits
37 *
38 * Bit 5 RXNE: Read data register not empty/RXFIFO not empty
39 * Bit 6 TC: Transmission complete
40 * Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full
41 * Bit 27 TXFE: TXFIFO threshold reached
42 */
43 #define USART_ISR_RXNE_RXFNE BIT(5)
44 #define USART_ISR_TC BIT(6)
45 #define USART_ISR_TXE_TXFNF BIT(7)
46 #define USART_ISR_TXFE BIT(27)
47
loc_chip_to_base(struct serial_chip * chip)48 static vaddr_t loc_chip_to_base(struct serial_chip *chip)
49 {
50 struct stm32_uart_pdata *pd = NULL;
51
52 pd = container_of(chip, struct stm32_uart_pdata, chip);
53
54 return io_pa_or_va(&pd->base, 1);
55 }
56
loc_flush(struct serial_chip * chip)57 static void loc_flush(struct serial_chip *chip)
58 {
59 vaddr_t base = loc_chip_to_base(chip);
60 uint64_t timeout = timeout_init_us(FLUSH_TIMEOUT_US);
61
62 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXFE))
63 if (timeout_elapsed(timeout))
64 return;
65 }
66
loc_putc(struct serial_chip * chip,int ch)67 static void loc_putc(struct serial_chip *chip, int ch)
68 {
69 vaddr_t base = loc_chip_to_base(chip);
70 uint64_t timeout = timeout_init_us(PUTC_TIMEOUT_US);
71
72 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF))
73 if (timeout_elapsed(timeout))
74 return;
75
76 io_write32(base + UART_REG_TDR, ch);
77 }
78
loc_have_rx_data(struct serial_chip * chip)79 static bool loc_have_rx_data(struct serial_chip *chip)
80 {
81 vaddr_t base = loc_chip_to_base(chip);
82
83 return io_read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE;
84 }
85
loc_getchar(struct serial_chip * chip)86 static int loc_getchar(struct serial_chip *chip)
87 {
88 vaddr_t base = loc_chip_to_base(chip);
89
90 while (!loc_have_rx_data(chip))
91 ;
92
93 return io_read32(base + UART_REG_RDR) & 0xff;
94 }
95
96 static const struct serial_ops stm32_uart_serial_ops = {
97 .flush = loc_flush,
98 .putc = loc_putc,
99 .have_rx_data = loc_have_rx_data,
100 .getchar = loc_getchar,
101
102 };
103 DECLARE_KEEP_PAGER(stm32_uart_serial_ops);
104
stm32_uart_init(struct stm32_uart_pdata * pd,vaddr_t base)105 void stm32_uart_init(struct stm32_uart_pdata *pd, vaddr_t base)
106 {
107 pd->base.pa = base;
108 pd->chip.ops = &stm32_uart_serial_ops;
109 }
110
111 #ifdef CFG_DT
register_secure_uart(struct stm32_uart_pdata * pd)112 static void register_secure_uart(struct stm32_uart_pdata *pd)
113 {
114 size_t n = 0;
115
116 stm32mp_register_secure_periph_iomem(pd->base.pa);
117 for (n = 0; n < pd->pinctrl_count; n++)
118 stm32mp_register_secure_gpio(pd->pinctrl[n].bank,
119 pd->pinctrl[n].pin);
120 }
121
register_non_secure_uart(struct stm32_uart_pdata * pd)122 static void register_non_secure_uart(struct stm32_uart_pdata *pd)
123 {
124 size_t n = 0;
125
126 stm32mp_register_non_secure_periph_iomem(pd->base.pa);
127 for (n = 0; n < pd->pinctrl_count; n++)
128 stm32mp_register_non_secure_gpio(pd->pinctrl[n].bank,
129 pd->pinctrl[n].pin);
130 }
131
stm32_uart_init_from_dt_node(void * fdt,int node)132 struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)
133 {
134 TEE_Result res = TEE_ERROR_GENERIC;
135 struct stm32_uart_pdata *pd = NULL;
136 struct dt_node_info info = { };
137 struct stm32_pinctrl *pinctrl_cfg = NULL;
138 int count = 0;
139
140 _fdt_fill_device_info(fdt, &info, node);
141
142 if (info.status == DT_STATUS_DISABLED)
143 return NULL;
144
145 assert(info.reg != DT_INFO_INVALID_REG &&
146 info.reg_size != DT_INFO_INVALID_REG_SIZE);
147
148 pd = calloc(1, sizeof(*pd));
149 if (!pd)
150 panic();
151
152 pd->chip.ops = &stm32_uart_serial_ops;
153 pd->base.pa = info.reg;
154 pd->secure = (info.status == DT_STATUS_OK_SEC);
155
156 res = clk_dt_get_by_index(fdt, node, 0, &pd->clock);
157 if (res) {
158 EMSG("Failed to get clock: %#"PRIx32, res);
159 panic();
160 }
161
162 res = clk_enable(pd->clock);
163 if (res)
164 panic();
165
166 assert(cpu_mmu_enabled());
167 pd->base.va = (vaddr_t)phys_to_virt(pd->base.pa,
168 pd->secure ? MEM_AREA_IO_SEC :
169 MEM_AREA_IO_NSEC, info.reg_size);
170
171 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0);
172 if (count < 0)
173 panic();
174
175 if (count) {
176 pinctrl_cfg = calloc(count, sizeof(*pinctrl_cfg));
177 if (!pinctrl_cfg)
178 panic();
179
180 stm32_pinctrl_fdt_get_pinctrl(fdt, node, pinctrl_cfg, count);
181 stm32_pinctrl_load_active_cfg(pinctrl_cfg, count);
182 }
183 pd->pinctrl = pinctrl_cfg;
184 pd->pinctrl_count = count;
185
186 if (pd->secure)
187 register_secure_uart(pd);
188 else
189 register_non_secure_uart(pd);
190
191 return pd;
192 }
193 #endif /*CFG_DT*/
194