1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (C) 2022, Vaisala Oyj
4  */
5 
6 #ifndef __DRIVERS_ZYNQMP_HUK_H__
7 #define __DRIVERS_ZYNQMP_HUK_H__
8 
9 /*
10  * Query Device DNA from the device
11  *
12  * Note: configured as weak so that it can be replaced with implementation to
13  * get read only PL Device DNA from FPGA array. This would need custom IP core
14  * for access.
15  *
16  * Both PS and PL Device DNA's have 96 bits.
17  *
18  * Xilinx recommends to use PL Device DNA for device identification.
19  *
20  * ref:
21  *
22  * 71342 - Zynq UltraScale+ Device - PS DNA is not write protected and is a
23  * different value than the PL DNA
24  *
25  * https://support.xilinx.com/s/article/71342
26  *
27  * @device_dna: Memory buffer to receive value of Device DNA
28  * @size: length of device_dna buffer (requires buffer of 12 bytes)
29  * Return a TEE_Result compliant status
30  */
31 TEE_Result tee_zynqmp_get_device_dna(uint8_t *device_dna, size_t size);
32 
33 #endif /* __DRIVERS_ZYNQMP_HUK_H__ */
34