1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3 * Copyright (c) 2014, STMicroelectronics International N.V.
4 * Copyright (c) 2021, Linaro Limited
5 * Copyright (c) 2022, Arm Limited.
6 */
7 #ifndef TEE_MMU_TYPES_H
8 #define TEE_MMU_TYPES_H
9
10 #include <stdint.h>
11 #include <sys/queue.h>
12 #include <util.h>
13
14 #define TEE_MATTR_VALID_BLOCK BIT(0)
15 #define TEE_MATTR_TABLE BIT(3)
16 #define TEE_MATTR_PR BIT(4)
17 #define TEE_MATTR_PW BIT(5)
18 #define TEE_MATTR_PX BIT(6)
19 #define TEE_MATTR_PRW (TEE_MATTR_PR | TEE_MATTR_PW)
20 #define TEE_MATTR_PRX (TEE_MATTR_PR | TEE_MATTR_PX)
21 #define TEE_MATTR_PRWX (TEE_MATTR_PRW | TEE_MATTR_PX)
22 #define TEE_MATTR_UR BIT(7)
23 #define TEE_MATTR_UW BIT(8)
24 #define TEE_MATTR_UX BIT(9)
25 #define TEE_MATTR_URW (TEE_MATTR_UR | TEE_MATTR_UW)
26 #define TEE_MATTR_URX (TEE_MATTR_UR | TEE_MATTR_UX)
27 #define TEE_MATTR_URWX (TEE_MATTR_URW | TEE_MATTR_UX)
28 #define TEE_MATTR_PROT_MASK \
29 (TEE_MATTR_PRWX | TEE_MATTR_URWX | TEE_MATTR_GUARDED)
30
31 #define TEE_MATTR_GLOBAL BIT(10)
32 #define TEE_MATTR_SECURE BIT(11)
33
34 #define TEE_MATTR_MEM_TYPE_MASK U(0x7)
35 #define TEE_MATTR_MEM_TYPE_SHIFT U(12)
36 /* These are shifted TEE_MATTR_MEM_TYPE_SHIFT */
37
38 /*
39 * Device-nGnRnE most restrictive (equivalent to Strongly Ordered memory
40 * in the ARMv7 architecture).
41 * https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Memory-types/Device-memory
42 *
43 * If an ARMv7 architecture operating system runs on a Cortex-A53 processor,
44 * the Device memory type matches the nGnRE encoding and the Strongly-Ordered
45 * memory type matches the nGnRnE memory type.
46 * https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Memory-types/Device-memory
47 */
48 #define TEE_MATTR_MEM_TYPE_DEV U(0) /* Device-nGnRE */
49 #define TEE_MATTR_MEM_TYPE_CACHED U(1)
50 #define TEE_MATTR_MEM_TYPE_STRONGLY_O U(2) /* Device-nGnRnE */
51 #define TEE_MATTR_MEM_TYPE_TAGGED U(3)
52
53 #define TEE_MATTR_GUARDED BIT(15)
54
55 /*
56 * Tags TA mappings which are only used during a single call (open session
57 * or invoke command parameters).
58 */
59 #define VM_FLAG_EPHEMERAL BIT(0)
60 /*
61 * Tags TA mappings that must not be removed (kernel mappings while in user
62 * mode).
63 */
64 #define VM_FLAG_PERMANENT BIT(1)
65 /* Tags TA mappings that may be shared with other TAs. */
66 #define VM_FLAG_SHAREABLE BIT(2)
67 /* Tags temporary mappings added to load the ldelf binary */
68 #define VM_FLAG_LDELF BIT(3)
69 /*
70 * The mapping should only be mapped read-only, not enforced by the vm_*
71 * functions.
72 */
73 #define VM_FLAG_READONLY BIT(4)
74
75 /*
76 * Set of flags used by tee_mmu_is_vbuf_inside_ta_private() and
77 * tee_mmu_is_vbuf_intersect_ta_private() to tell if a certain region is
78 * mapping TA internal memory or not.
79 */
80 #define VM_FLAGS_NONPRIV (VM_FLAG_EPHEMERAL | \
81 VM_FLAG_PERMANENT | \
82 VM_FLAG_SHAREABLE)
83
84 struct tee_mmap_region {
85 unsigned int type; /* enum teecore_memtypes */
86 unsigned int region_size;
87 paddr_t pa;
88 vaddr_t va;
89 size_t size;
90 uint32_t attr; /* TEE_MATTR_* above */
91 };
92
93 struct vm_region {
94 struct mobj *mobj;
95 size_t offset;
96 vaddr_t va;
97 size_t size;
98 uint16_t attr; /* TEE_MATTR_* above */
99 uint16_t flags; /* VM_FLAGS_* above */
100 TAILQ_ENTRY(vm_region) link;
101 };
102
103 enum vm_paged_region_type {
104 PAGED_REGION_TYPE_RO,
105 PAGED_REGION_TYPE_RW,
106 PAGED_REGION_TYPE_LOCK,
107 };
108
109 struct vm_paged_region {
110 struct fobj *fobj;
111 size_t fobj_pgoffs;
112 enum vm_paged_region_type type;
113 uint32_t flags;
114 vaddr_t base;
115 size_t size;
116 struct pgt **pgt_array;
117 TAILQ_ENTRY(vm_paged_region) link;
118 TAILQ_ENTRY(vm_paged_region) fobj_link;
119 };
120
121 TAILQ_HEAD(vm_paged_region_head, vm_paged_region);
122 TAILQ_HEAD(vm_region_head, vm_region);
123
124 struct vm_info {
125 struct vm_region_head regions;
126 unsigned int asid;
127 };
128
mattr_perm_to_str(char * str,size_t size,uint32_t attr)129 static inline void mattr_perm_to_str(char *str, size_t size, uint32_t attr)
130 {
131 if (size < 7)
132 return;
133
134 str[0] = (attr & TEE_MATTR_UR) ? 'r' : '-';
135 str[1] = (attr & TEE_MATTR_UW) ? 'w' : '-';
136 str[2] = (attr & TEE_MATTR_UX) ? 'x' : '-';
137 str[3] = (attr & TEE_MATTR_PR) ? 'R' : '-';
138 str[4] = (attr & TEE_MATTR_PW) ? 'W' : '-';
139 str[5] = (attr & TEE_MATTR_PX) ? 'X' : '-';
140 str[6] = '\0';
141 }
142
mattr_is_cached(uint32_t mattr)143 static inline bool mattr_is_cached(uint32_t mattr)
144 {
145 uint32_t mem_type = (mattr >> TEE_MATTR_MEM_TYPE_SHIFT) &
146 TEE_MATTR_MEM_TYPE_MASK;
147
148 return mem_type == TEE_MATTR_MEM_TYPE_CACHED ||
149 mem_type == TEE_MATTR_MEM_TYPE_TAGGED;
150 }
151 #endif
152