1#
2# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3#
4# SPDX-License-Identifier: GPL-2.0-only
5#
6
7cmake_minimum_required(VERSION 3.7.2)
8
9config_string(
10    KernelPTLevels PT_LEVELS "Number of page \
11    table levels for RISC-V depends on the mode. For example there are: \
12    2, 3 and 4 levels on Sv32, Sv39, Sv48 RISC-V paging modes respectively."
13    DEFAULT 3 UNDEF_DISABLED
14    UNQUOTE
15    DEPENDS "KernelArchRiscV"
16)
17
18config_option(
19    KernelRiscvExtF RISCV_EXT_F "RISC-V extension for single-precision floating-point"
20    DEFAULT OFF
21    DEPENDS "KernelArchRiscV"
22)
23
24config_option(
25    KernelRiscvExtD RISCV_EXT_D "RISC-V extension for double-precision floating-point"
26    DEFAULT OFF
27    DEPENDS "KernelArchRiscV"
28)
29
30# Until RISC-V has instructions to count leading/trailing zeros, we provide
31# library implementations. Platforms that implement the bit manipulation
32# extension can override these settings to remove the library functions from
33# the image.
34# In the verified configurations, we additionally define KernelClzNoBuiltin and
35# KernelCtzNoBuiltin to expose the library implementations to verification.
36# However, since the NoBuiltin options force the use of the library functions
37# even when the platform has sutiable inline assembly, we do not make these the
38# default.
39if(KernelWordSize EQUAL 32)
40    set(KernelClz32 ON CACHE BOOL "")
41    set(KernelCtz32 ON CACHE BOOL "")
42    if(KernelIsMCS)
43        # Used for long division in timer calculations.
44        set(KernelClz64 ON CACHE BOOL "")
45    endif()
46elseif(KernelWordSize EQUAL 64)
47    set(KernelClz64 ON CACHE BOOL "")
48    set(KernelCtz64 ON CACHE BOOL "")
49endif()
50
51if(KernelSel4ArchRiscV32)
52    set(KernelPTLevels 2 CACHE STRING "" FORCE)
53endif()
54if(KernelPTLevels EQUAL 2)
55    if(KernelSel4ArchRiscV32)
56        # seL4 on RISCV32 uses 32-bit ints for addresses,
57        # so limit the maximum paddr to 32-bits.
58        math(EXPR KernelPaddrUserTop "(1 << 32) - 1")
59    else()
60        math(EXPR KernelPaddrUserTop "1 << 34")
61    endif()
62elseif(KernelPTLevels EQUAL 3)
63    # RISC-V technically supports 56-bit paddrs,
64    # but structures.bf limits us to using 39 of those bits.
65    math(EXPR KernelPaddrUserTop "1 << 39")
66elseif(KernelPTLevels EQUAL 4)
67    math(EXPR KernelPaddrUserTop "1 << 56")
68endif()
69
70if(KernelRiscvExtD)
71    set(KernelRiscvExtF ON)
72    set(KernelHaveFPU ON)
73endif()
74
75if(KernelRiscvExtF)
76    set(KernelHaveFPU ON)
77endif()
78
79# This is not supported on RISC-V
80set(KernelHardwareDebugAPIUnsupported ON CACHE INTERNAL "")
81
82add_sources(
83    DEP "KernelArchRiscV"
84    PREFIX src/arch/riscv
85    CFILES
86        c_traps.c
87        idle.c
88        api/faults.c
89        api/benchmark.c
90        kernel/boot.c
91        kernel/thread.c
92        kernel/vspace.c
93        machine/capdl.c
94        machine/hardware.c
95        machine/registerset.c
96        machine/io.c
97        machine/fpu.c
98        model/statedata.c
99        object/interrupt.c
100        object/objecttype.c
101        object/tcb.c
102        smp/ipi.c
103    ASMFILES halt.S head.S traps.S
104)
105
106add_bf_source_old("KernelArchRiscV" "structures.bf" "include/arch/riscv" "arch/object")
107