1/*
2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#pragma once
8
9#include <config.h>
10
11#define TIMER_CLOCK_HZ ULL_CONST(@CONFIGURE_TIMER_FREQUENCY@)
12
13#include <machine/interrupt.h>
14
15/*
16 * seL4 assigns all IRQs global interrupt numbers that are used in interrupt
17 * invocations. On RISC-V we have 3 different types of interrupts: core timer,
18 * core software generated, and global external IRQs delivered through the PLIC.
19 * Only global external interrupts are available from user level and so it is
20 * nice to be able to match PLIC IRQ numbers to seL4 IRQ numbers. The PLIC uses
21 * IRQ 0 to refer to no IRQ pending and so we can also use 0 for irqInvalid in
22 * the global IRQ number space and not have any aliasing issues. We then place
23 * the kernel timer interrupts after the last PLIC interrupt and intend on
24 * placing software generated interrupts after this in the future. As the kernel
25 * timer and SGI interrupts are never seen outside of the kernel, it doesn't
26 * matter what number they get assigned to as we can refer to them by their enum
27 * field name.
28 */
29enum IRQConstants {
30    PLIC_IRQ_OFFSET = 0,
31    PLIC_MAX_IRQ = PLIC_IRQ_OFFSET + (@CONFIGURE_PLIC_MAX_NUM_INT@),
32#ifdef ENABLE_SMP_SUPPORT
33    INTERRUPT_IPI_0,
34    INTERRUPT_IPI_1,
35#endif
36    KERNEL_TIMER_IRQ,
37    maxIRQ = KERNEL_TIMER_IRQ,
38} platform_interrupt_t;
39
40enum irqNumbers {
41    irqInvalid = 0
42};
43
44#define IRQ_CNODE_SLOT_BITS (@CONFIGURE_IRQ_SLOT_BITS@)
45
46#include <@CONFIGURE_INTERRUPT_CONTROLLER@>
47