1 /*
2 * Copyright 2015, DornerWorks
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7 #include <arch/machine.h>
8
readACR(void)9 static inline word_t readACR(void)
10 {
11 word_t ACR;
12 asm volatile("mrc p15,0,%0,c1,c0,1" : "=r"(ACR));
13 return ACR;
14 }
15
writeACR(word_t ACR)16 static inline void writeACR(word_t ACR)
17 {
18 asm volatile("mcr p15,0,%0,c1,c0,1" : : "r"(ACR));
19 }
20
initL2Cache(void)21 void initL2Cache(void)
22 {
23 cleanInvalidateL1Caches();
24
25 /*
26 * Set the L2EN bit in the Auxially Control Register.
27 *
28 * We assume the C bit is already set in the system control register (from
29 * head.S), and that the L2 Cache Auxilliary Control Register is correct
30 * (as per reset).
31 */
32 writeACR(readACR() | 0x2);
33
34 cleanInvalidateL1Caches();
35 }
36
plat_cleanL2Range(paddr_t start,paddr_t end)37 void plat_cleanL2Range(paddr_t start, paddr_t end) {}
plat_invalidateL2Range(paddr_t start,paddr_t end)38 void plat_invalidateL2Range(paddr_t start, paddr_t end) {}
plat_cleanInvalidateL2Range(paddr_t start,paddr_t end)39 void plat_cleanInvalidateL2Range(paddr_t start, paddr_t end) {}
plat_cleanInvalidateL2Cache(void)40 void plat_cleanInvalidateL2Cache(void) {}
41