1/*
2 * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7/ {
8	/*
9	 * Explicitly specify the boot cpu (the first LITTLE core)
10	 * so we pick the right PMU interrupt.
11	 * Note: "On Exynos5422 booting cluster (big or LITTLE) is chosen by IROM code by reading
12	 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
13	 * from the LITTLE: Cortex-A7."
14	 */
15	chosen {
16		seL4,boot-cpu = <&{/cpus/cpu@100}>;
17		seL4,elfloader-devices =
18		    "serial2";
19		seL4,kernel-devices =
20		    "serial2",
21		    &{/soc/interrupt-controller@10481000},
22		    &{/soc/mct@101c0000},
23		    &{/timer};
24	};
25
26	/* The architecture timer on exynos5 depends on the MCT, but it is there. */
27	timer {
28		compatible = "arm,armv7-timer";
29		interrupts = <0x1 0xd 0xf08>, <0x1 0xe 0xf08>, <0x1 0xb 0xf08>, <0x1 0xa 0xf08>;
30		clock-frequency = <0x16e3600>;
31	};
32
33	/* HACK: 0xe0000000..0xff000000 is the largest contiguous region
34	 * in the kernel window; we clamp to that and discard memory
35	 * after the ASID PD hole (0xff200000..0xfff00000). This is a
36	 * workaround for userspace tools (hardware_gen, elfloader, etc)
37	 * which are not yet aware of the memory hole. */
38	memory@40000000 {
39		reg = <0x60000000 0x1f000000>;
40	};
41
42	vm-memory@40000000 {
43		reg = <0x40000000 0x20000000>;
44	};
45};
46