1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	compatible = "ti,am335x-bone-black\0ti,am335x-bone\0ti,am33xx";
15	interrupt-parent = < 0x01 >;
16	#address-cells = < 0x01 >;
17	#size-cells = < 0x01 >;
18	model = "TI AM335x BeagleBone Black";
19
20	chosen {
21		stdout-path = "/ocp/serial@44e09000";
22	};
23
24	aliases {
25		i2c0 = "/ocp/i2c@44e0b000";
26		i2c1 = "/ocp/i2c@4802a000";
27		i2c2 = "/ocp/i2c@4819c000";
28		serial0 = "/ocp/serial@44e09000";
29		serial1 = "/ocp/serial@48022000";
30		serial2 = "/ocp/serial@48024000";
31		serial3 = "/ocp/serial@481a6000";
32		serial4 = "/ocp/serial@481a8000";
33		serial5 = "/ocp/serial@481aa000";
34		d-can0 = "/ocp/can@481cc000";
35		d-can1 = "/ocp/can@481d0000";
36		usb0 = "/ocp/usb@47400000/usb@47401000";
37		usb1 = "/ocp/usb@47400000/usb@47401800";
38		phy0 = "/ocp/usb@47400000/usb-phy@47401300";
39		phy1 = "/ocp/usb@47400000/usb-phy@47401b00";
40		ethernet0 = "/ocp/ethernet@4a100000/slave@4a100200";
41		ethernet1 = "/ocp/ethernet@4a100000/slave@4a100300";
42		spi0 = "/ocp/spi@48030000";
43		spi1 = "/ocp/spi@481a0000";
44	};
45
46	cpus {
47		#address-cells = < 0x01 >;
48		#size-cells = < 0x00 >;
49
50		cpu@0 {
51			compatible = "arm,cortex-a8";
52			device_type = "cpu";
53			reg = < 0x00 >;
54			operating-points-v2 = < 0x02 >;
55			clocks = < 0x03 >;
56			clock-names = "cpu";
57			clock-latency = < 0x493e0 >;
58			cpu0-supply = < 0x04 >;
59		};
60	};
61
62	opp-table {
63		compatible = "operating-points-v2-ti-cpu";
64		syscon = < 0x05 >;
65		phandle = < 0x02 >;
66
67		opp50-300000000 {
68			opp-hz = < 0x00 0x11e1a300 >;
69			opp-microvolt = < 0xe7ef0 0xe34b8 0xec928 >;
70			opp-supported-hw = < 0x06 0x10 >;
71			opp-suspend;
72		};
73
74		opp100-275000000 {
75			opp-hz = < 0x00 0x10642ac0 >;
76			opp-microvolt = < 0x10c8e0 0x1072f0 0x111ed0 >;
77			opp-supported-hw = < 0x01 0xff >;
78			opp-suspend;
79		};
80
81		opp100-300000000 {
82			opp-hz = < 0x00 0x11e1a300 >;
83			opp-microvolt = < 0x10c8e0 0x1072f0 0x111ed0 >;
84			opp-supported-hw = < 0x06 0x20 >;
85			opp-suspend;
86		};
87
88		opp100-500000000 {
89			opp-hz = < 0x00 0x1dcd6500 >;
90			opp-microvolt = < 0x10c8e0 0x1072f0 0x111ed0 >;
91			opp-supported-hw = < 0x01 0xffff >;
92		};
93
94		opp100-600000000 {
95			opp-hz = < 0x00 0x23c34600 >;
96			opp-microvolt = < 0x10c8e0 0x1072f0 0x111ed0 >;
97			opp-supported-hw = < 0x06 0x40 >;
98		};
99
100		opp120-600000000 {
101			opp-hz = < 0x00 0x23c34600 >;
102			opp-microvolt = < 0x124f80 0x11f1c0 0x12ad40 >;
103			opp-supported-hw = < 0x01 0xffff >;
104		};
105
106		opp120-720000000 {
107			opp-hz = < 0x00 0x2aea5400 >;
108			opp-microvolt = < 0x124f80 0x11f1c0 0x12ad40 >;
109			opp-supported-hw = < 0x06 0x80 >;
110		};
111
112		oppturbo-720000000 {
113			opp-hz = < 0x00 0x2aea5400 >;
114			opp-microvolt = < 0x1339e0 0x12d770 0x139c50 >;
115			opp-supported-hw = < 0x01 0xffff >;
116		};
117
118		oppturbo-800000000 {
119			opp-hz = < 0x00 0x2faf0800 >;
120			opp-microvolt = < 0x1339e0 0x12d770 0x139c50 >;
121			opp-supported-hw = < 0x06 0x100 >;
122		};
123
124		oppnitro-1000000000 {
125			opp-hz = < 0x00 0x3b9aca00 >;
126			opp-microvolt = < 0x1437c8 0x13d044 0x149f4c >;
127			opp-supported-hw = < 0x06 0x100 >;
128		};
129	};
130
131	pmu@4b000000 {
132		compatible = "arm,cortex-a8-pmu";
133		interrupts = < 0x03 >;
134		reg = < 0x4b000000 0x1000000 >;
135		ti,hwmods = "debugss";
136	};
137
138	soc {
139		compatible = "ti,omap-infra";
140
141		mpu {
142			compatible = "ti,omap3-mpu";
143			ti,hwmods = "mpu";
144			pm-sram = < 0x06 0x07 >;
145		};
146	};
147
148	ocp {
149		compatible = "simple-bus";
150		#address-cells = < 0x01 >;
151		#size-cells = < 0x01 >;
152		ranges;
153		ti,hwmods = "l3_main";
154
155		l4_wkup@44c00000 {
156			compatible = "ti,am3-l4-wkup\0simple-bus";
157			#address-cells = < 0x01 >;
158			#size-cells = < 0x01 >;
159			ranges = < 0x00 0x44c00000 0x280000 >;
160
161			wkup_m3@100000 {
162				compatible = "ti,am3352-wkup-m3";
163				reg = < 0x100000 0x4000 0x180000 0x2000 >;
164				reg-names = "umem\0dmem";
165				ti,hwmods = "wkup_m3";
166				ti,pm-firmware = "am335x-pm-firmware.elf";
167				phandle = < 0x24 >;
168			};
169
170			prcm@200000 {
171				compatible = "ti,am3-prcm\0simple-bus";
172				reg = < 0x200000 0x4000 >;
173				#address-cells = < 0x01 >;
174				#size-cells = < 0x01 >;
175				ranges = < 0x00 0x200000 0x4000 >;
176
177				clocks {
178					#address-cells = < 0x01 >;
179					#size-cells = < 0x00 >;
180
181					clk_32768_ck {
182						#clock-cells = < 0x00 >;
183						compatible = "fixed-clock";
184						clock-frequency = < 0x8000 >;
185						phandle = < 0x17 >;
186					};
187
188					clk_rc32k_ck {
189						#clock-cells = < 0x00 >;
190						compatible = "fixed-clock";
191						clock-frequency = < 0x7d00 >;
192						phandle = < 0x16 >;
193					};
194
195					virt_19200000_ck {
196						#clock-cells = < 0x00 >;
197						compatible = "fixed-clock";
198						clock-frequency = < 0x124f800 >;
199						phandle = < 0x1f >;
200					};
201
202					virt_24000000_ck {
203						#clock-cells = < 0x00 >;
204						compatible = "fixed-clock";
205						clock-frequency = < 0x16e3600 >;
206						phandle = < 0x20 >;
207					};
208
209					virt_25000000_ck {
210						#clock-cells = < 0x00 >;
211						compatible = "fixed-clock";
212						clock-frequency = < 0x17d7840 >;
213						phandle = < 0x21 >;
214					};
215
216					virt_26000000_ck {
217						#clock-cells = < 0x00 >;
218						compatible = "fixed-clock";
219						clock-frequency = < 0x18cba80 >;
220						phandle = < 0x22 >;
221					};
222
223					tclkin_ck {
224						#clock-cells = < 0x00 >;
225						compatible = "fixed-clock";
226						clock-frequency = < 0xb71b00 >;
227						phandle = < 0x15 >;
228					};
229
230					dpll_core_ck@490 {
231						#clock-cells = < 0x00 >;
232						compatible = "ti,am3-dpll-core-clock";
233						clocks = < 0x08 0x08 >;
234						reg = < 0x490 0x45c 0x468 >;
235						phandle = < 0x09 >;
236					};
237
238					dpll_core_x2_ck {
239						#clock-cells = < 0x00 >;
240						compatible = "ti,am3-dpll-x2-clock";
241						clocks = < 0x09 >;
242						phandle = < 0x0a >;
243					};
244
245					dpll_core_m4_ck@480 {
246						#clock-cells = < 0x00 >;
247						compatible = "ti,divider-clock";
248						clocks = < 0x0a >;
249						ti,max-div = < 0x1f >;
250						reg = < 0x480 >;
251						ti,index-starts-at-one;
252						phandle = < 0x11 >;
253					};
254
255					dpll_core_m5_ck@484 {
256						#clock-cells = < 0x00 >;
257						compatible = "ti,divider-clock";
258						clocks = < 0x0a >;
259						ti,max-div = < 0x1f >;
260						reg = < 0x484 >;
261						ti,index-starts-at-one;
262						phandle = < 0x19 >;
263					};
264
265					dpll_core_m6_ck@4d8 {
266						#clock-cells = < 0x00 >;
267						compatible = "ti,divider-clock";
268						clocks = < 0x0a >;
269						ti,max-div = < 0x1f >;
270						reg = < 0x4d8 >;
271						ti,index-starts-at-one;
272					};
273
274					dpll_mpu_ck@488 {
275						#clock-cells = < 0x00 >;
276						compatible = "ti,am3-dpll-clock";
277						clocks = < 0x08 0x08 >;
278						reg = < 0x488 0x420 0x42c >;
279						phandle = < 0x03 >;
280					};
281
282					dpll_mpu_m2_ck@4a8 {
283						#clock-cells = < 0x00 >;
284						compatible = "ti,divider-clock";
285						clocks = < 0x03 >;
286						ti,max-div = < 0x1f >;
287						reg = < 0x4a8 >;
288						ti,index-starts-at-one;
289					};
290
291					dpll_ddr_ck@494 {
292						#clock-cells = < 0x00 >;
293						compatible = "ti,am3-dpll-no-gate-clock";
294						clocks = < 0x08 0x08 >;
295						reg = < 0x494 0x434 0x440 >;
296						phandle = < 0x0b >;
297					};
298
299					dpll_ddr_m2_ck@4a0 {
300						#clock-cells = < 0x00 >;
301						compatible = "ti,divider-clock";
302						clocks = < 0x0b >;
303						ti,max-div = < 0x1f >;
304						reg = < 0x4a0 >;
305						ti,index-starts-at-one;
306						phandle = < 0x0c >;
307					};
308
309					dpll_ddr_m2_div2_ck {
310						#clock-cells = < 0x00 >;
311						compatible = "fixed-factor-clock";
312						clocks = < 0x0c >;
313						clock-mult = < 0x01 >;
314						clock-div = < 0x02 >;
315					};
316
317					dpll_disp_ck@498 {
318						#clock-cells = < 0x00 >;
319						compatible = "ti,am3-dpll-no-gate-clock";
320						clocks = < 0x08 0x08 >;
321						reg = < 0x498 0x448 0x454 >;
322						phandle = < 0x0d >;
323					};
324
325					dpll_disp_m2_ck@4a4 {
326						#clock-cells = < 0x00 >;
327						compatible = "ti,divider-clock";
328						clocks = < 0x0d >;
329						ti,max-div = < 0x1f >;
330						reg = < 0x4a4 >;
331						ti,index-starts-at-one;
332						ti,set-rate-parent;
333						phandle = < 0x13 >;
334					};
335
336					dpll_per_ck@48c {
337						#clock-cells = < 0x00 >;
338						compatible = "ti,am3-dpll-no-gate-j-type-clock";
339						clocks = < 0x08 0x08 >;
340						reg = < 0x48c 0x470 0x49c >;
341						phandle = < 0x0e >;
342					};
343
344					dpll_per_m2_ck@4ac {
345						#clock-cells = < 0x00 >;
346						compatible = "ti,divider-clock";
347						clocks = < 0x0e >;
348						ti,max-div = < 0x1f >;
349						reg = < 0x4ac >;
350						ti,index-starts-at-one;
351						phandle = < 0x0f >;
352					};
353
354					dpll_per_m2_div4_wkupdm_ck {
355						#clock-cells = < 0x00 >;
356						compatible = "fixed-factor-clock";
357						clocks = < 0x0f >;
358						clock-mult = < 0x01 >;
359						clock-div = < 0x04 >;
360					};
361
362					dpll_per_m2_div4_ck {
363						#clock-cells = < 0x00 >;
364						compatible = "fixed-factor-clock";
365						clocks = < 0x0f >;
366						clock-mult = < 0x01 >;
367						clock-div = < 0x04 >;
368					};
369
370					clk_24mhz {
371						#clock-cells = < 0x00 >;
372						compatible = "fixed-factor-clock";
373						clocks = < 0x0f >;
374						clock-mult = < 0x01 >;
375						clock-div = < 0x08 >;
376						phandle = < 0x10 >;
377					};
378
379					clkdiv32k_ck {
380						#clock-cells = < 0x00 >;
381						compatible = "fixed-factor-clock";
382						clocks = < 0x10 >;
383						clock-mult = < 0x01 >;
384						clock-div = < 0x2dc >;
385					};
386
387					l3_gclk {
388						#clock-cells = < 0x00 >;
389						compatible = "fixed-factor-clock";
390						clocks = < 0x11 >;
391						clock-mult = < 0x01 >;
392						clock-div = < 0x01 >;
393						phandle = < 0x12 >;
394					};
395
396					pruss_ocp_gclk@530 {
397						#clock-cells = < 0x00 >;
398						compatible = "ti,mux-clock";
399						clocks = < 0x12 0x13 >;
400						reg = < 0x530 >;
401					};
402
403					mmu_fck@914 {
404						#clock-cells = < 0x00 >;
405						compatible = "ti,gate-clock";
406						clocks = < 0x11 >;
407						ti,bit-shift = < 0x01 >;
408						reg = < 0x914 >;
409					};
410
411					timer1_fck@528 {
412						#clock-cells = < 0x00 >;
413						compatible = "ti,mux-clock";
414						clocks = < 0x08 0x14 0x138 0x00 0x15 0x16 0x17 >;
415						reg = < 0x528 >;
416						phandle = < 0x39 >;
417					};
418
419					timer2_fck@508 {
420						#clock-cells = < 0x00 >;
421						compatible = "ti,mux-clock";
422						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
423						reg = < 0x508 >;
424						phandle = < 0x3a >;
425					};
426
427					timer3_fck@50c {
428						#clock-cells = < 0x00 >;
429						compatible = "ti,mux-clock";
430						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
431						reg = < 0x50c >;
432					};
433
434					timer4_fck@510 {
435						#clock-cells = < 0x00 >;
436						compatible = "ti,mux-clock";
437						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
438						reg = < 0x510 >;
439					};
440
441					timer5_fck@518 {
442						#clock-cells = < 0x00 >;
443						compatible = "ti,mux-clock";
444						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
445						reg = < 0x518 >;
446					};
447
448					timer6_fck@51c {
449						#clock-cells = < 0x00 >;
450						compatible = "ti,mux-clock";
451						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
452						reg = < 0x51c >;
453					};
454
455					timer7_fck@504 {
456						#clock-cells = < 0x00 >;
457						compatible = "ti,mux-clock";
458						clocks = < 0x15 0x08 0x14 0x138 0x00 >;
459						reg = < 0x504 >;
460					};
461
462					usbotg_fck@47c {
463						#clock-cells = < 0x00 >;
464						compatible = "ti,gate-clock";
465						clocks = < 0x0e >;
466						ti,bit-shift = < 0x08 >;
467						reg = < 0x47c >;
468					};
469
470					dpll_core_m4_div2_ck {
471						#clock-cells = < 0x00 >;
472						compatible = "fixed-factor-clock";
473						clocks = < 0x11 >;
474						clock-mult = < 0x01 >;
475						clock-div = < 0x02 >;
476						phandle = < 0x18 >;
477					};
478
479					ieee5000_fck@e4 {
480						#clock-cells = < 0x00 >;
481						compatible = "ti,gate-clock";
482						clocks = < 0x18 >;
483						ti,bit-shift = < 0x01 >;
484						reg = < 0xe4 >;
485					};
486
487					wdt1_fck@538 {
488						#clock-cells = < 0x00 >;
489						compatible = "ti,mux-clock";
490						clocks = < 0x16 0x14 0x138 0x00 >;
491						reg = < 0x538 >;
492					};
493
494					l4_rtc_gclk {
495						#clock-cells = < 0x00 >;
496						compatible = "fixed-factor-clock";
497						clocks = < 0x11 >;
498						clock-mult = < 0x01 >;
499						clock-div = < 0x02 >;
500					};
501
502					l4hs_gclk {
503						#clock-cells = < 0x00 >;
504						compatible = "fixed-factor-clock";
505						clocks = < 0x11 >;
506						clock-mult = < 0x01 >;
507						clock-div = < 0x01 >;
508					};
509
510					l3s_gclk {
511						#clock-cells = < 0x00 >;
512						compatible = "fixed-factor-clock";
513						clocks = < 0x18 >;
514						clock-mult = < 0x01 >;
515						clock-div = < 0x01 >;
516					};
517
518					l4fw_gclk {
519						#clock-cells = < 0x00 >;
520						compatible = "fixed-factor-clock";
521						clocks = < 0x18 >;
522						clock-mult = < 0x01 >;
523						clock-div = < 0x01 >;
524					};
525
526					l4ls_gclk {
527						#clock-cells = < 0x00 >;
528						compatible = "fixed-factor-clock";
529						clocks = < 0x18 >;
530						clock-mult = < 0x01 >;
531						clock-div = < 0x01 >;
532						phandle = < 0x23 >;
533					};
534
535					sysclk_div_ck {
536						#clock-cells = < 0x00 >;
537						compatible = "fixed-factor-clock";
538						clocks = < 0x11 >;
539						clock-mult = < 0x01 >;
540						clock-div = < 0x01 >;
541					};
542
543					cpsw_125mhz_gclk {
544						#clock-cells = < 0x00 >;
545						compatible = "fixed-factor-clock";
546						clocks = < 0x19 >;
547						clock-mult = < 0x01 >;
548						clock-div = < 0x02 >;
549						phandle = < 0x43 >;
550					};
551
552					cpsw_cpts_rft_clk@520 {
553						#clock-cells = < 0x00 >;
554						compatible = "ti,mux-clock";
555						clocks = < 0x19 0x11 >;
556						reg = < 0x520 >;
557						phandle = < 0x44 >;
558					};
559
560					gpio0_dbclk_mux_ck@53c {
561						#clock-cells = < 0x00 >;
562						compatible = "ti,mux-clock";
563						clocks = < 0x16 0x17 0x14 0x138 0x00 >;
564						reg = < 0x53c >;
565					};
566
567					lcd_gclk@534 {
568						#clock-cells = < 0x00 >;
569						compatible = "ti,mux-clock";
570						clocks = < 0x13 0x19 0x0f >;
571						reg = < 0x534 >;
572						ti,set-rate-parent;
573						phandle = < 0x1b >;
574					};
575
576					mmc_clk {
577						#clock-cells = < 0x00 >;
578						compatible = "fixed-factor-clock";
579						clocks = < 0x0f >;
580						clock-mult = < 0x01 >;
581						clock-div = < 0x02 >;
582					};
583
584					gfx_fclk_clksel_ck@52c {
585						#clock-cells = < 0x00 >;
586						compatible = "ti,mux-clock";
587						clocks = < 0x11 0x0f >;
588						ti,bit-shift = < 0x01 >;
589						reg = < 0x52c >;
590						phandle = < 0x1a >;
591					};
592
593					gfx_fck_div_ck@52c {
594						#clock-cells = < 0x00 >;
595						compatible = "ti,divider-clock";
596						clocks = < 0x1a >;
597						reg = < 0x52c >;
598						ti,max-div = < 0x02 >;
599					};
600
601					sysclkout_pre_ck@700 {
602						#clock-cells = < 0x00 >;
603						compatible = "ti,mux-clock";
604						clocks = < 0x17 0x12 0x0c 0x0f 0x1b >;
605						reg = < 0x700 >;
606						phandle = < 0x1c >;
607					};
608
609					clkout2_div_ck@700 {
610						#clock-cells = < 0x00 >;
611						compatible = "ti,divider-clock";
612						clocks = < 0x1c >;
613						ti,bit-shift = < 0x03 >;
614						ti,max-div = < 0x08 >;
615						reg = < 0x700 >;
616						phandle = < 0x1d >;
617					};
618
619					clkout2_ck@700 {
620						#clock-cells = < 0x00 >;
621						compatible = "ti,gate-clock";
622						clocks = < 0x1d >;
623						ti,bit-shift = < 0x07 >;
624						reg = < 0x700 >;
625					};
626				};
627
628				clockdomains {
629				};
630
631				l4_per_cm@0 {
632					compatible = "ti,omap4-cm";
633					reg = < 0x00 0x200 >;
634					#address-cells = < 0x01 >;
635					#size-cells = < 0x01 >;
636					ranges = < 0x00 0x00 0x200 >;
637
638					clk@14 {
639						compatible = "ti,clkctrl";
640						reg = < 0x14 0x13c >;
641						#clock-cells = < 0x02 >;
642						phandle = < 0x14 >;
643					};
644				};
645
646				l4_wkup_cm@400 {
647					compatible = "ti,omap4-cm";
648					reg = < 0x400 0x100 >;
649					#address-cells = < 0x01 >;
650					#size-cells = < 0x01 >;
651					ranges = < 0x00 0x400 0x100 >;
652
653					clk@4 {
654						compatible = "ti,clkctrl";
655						reg = < 0x04 0xd4 >;
656						#clock-cells = < 0x02 >;
657					};
658				};
659
660				mpu_cm@600 {
661					compatible = "ti,omap4-cm";
662					reg = < 0x600 0x100 >;
663					#address-cells = < 0x01 >;
664					#size-cells = < 0x01 >;
665					ranges = < 0x00 0x600 0x100 >;
666
667					clk@4 {
668						compatible = "ti,clkctrl";
669						reg = < 0x04 0x04 >;
670						#clock-cells = < 0x02 >;
671					};
672				};
673
674				l4_rtc_cm@800 {
675					compatible = "ti,omap4-cm";
676					reg = < 0x800 0x100 >;
677					#address-cells = < 0x01 >;
678					#size-cells = < 0x01 >;
679					ranges = < 0x00 0x800 0x100 >;
680
681					clk@0 {
682						compatible = "ti,clkctrl";
683						reg = < 0x00 0x04 >;
684						#clock-cells = < 0x02 >;
685					};
686				};
687
688				gfx_l3_cm@900 {
689					compatible = "ti,omap4-cm";
690					reg = < 0x900 0x100 >;
691					#address-cells = < 0x01 >;
692					#size-cells = < 0x01 >;
693					ranges = < 0x00 0x900 0x100 >;
694
695					clk@4 {
696						compatible = "ti,clkctrl";
697						reg = < 0x04 0x04 >;
698						#clock-cells = < 0x02 >;
699					};
700				};
701
702				l4_cefuse_cm@a00 {
703					compatible = "ti,omap4-cm";
704					reg = < 0xa00 0x100 >;
705					#address-cells = < 0x01 >;
706					#size-cells = < 0x01 >;
707					ranges = < 0x00 0xa00 0x100 >;
708
709					clk@20 {
710						compatible = "ti,clkctrl";
711						reg = < 0x20 0x04 >;
712						#clock-cells = < 0x02 >;
713					};
714				};
715			};
716
717			scm@210000 {
718				compatible = "ti,am3-scm\0simple-bus";
719				reg = < 0x210000 0x2000 >;
720				#address-cells = < 0x01 >;
721				#size-cells = < 0x01 >;
722				#pinctrl-cells = < 0x01 >;
723				ranges = < 0x00 0x210000 0x2000 >;
724
725				pinmux@800 {
726					compatible = "pinctrl-single";
727					reg = < 0x800 0x238 >;
728					#address-cells = < 0x01 >;
729					#size-cells = < 0x00 >;
730					#pinctrl-cells = < 0x01 >;
731					pinctrl-single,register-width = < 0x20 >;
732					pinctrl-single,function-mask = < 0x7f >;
733					pinctrl-names = "default";
734					pinctrl-0 = < 0x1e >;
735
736					user_leds_s0 {
737						pinctrl-single,pins = < 0x54 0x07 0x58 0x17 0x5c 0x07 0x60 0x17 >;
738						phandle = < 0x4c >;
739					};
740
741					pinmux_i2c0_pins {
742						pinctrl-single,pins = < 0x188 0x30 0x18c 0x30 >;
743						phandle = < 0x2c >;
744					};
745
746					pinmux_i2c2_pins {
747						pinctrl-single,pins = < 0x178 0x33 0x17c 0x33 >;
748						phandle = < 0x31 >;
749					};
750
751					pinmux_uart0_pins {
752						pinctrl-single,pins = < 0x170 0x30 0x174 0x00 >;
753						phandle = < 0x2b >;
754					};
755
756					pinmux_clkout2_pin {
757						pinctrl-single,pins = < 0x1b4 0x03 >;
758						phandle = < 0x1e >;
759					};
760
761					cpsw_default {
762						pinctrl-single,pins = < 0x110 0x30 0x114 0x00 0x118 0x30 0x11c 0x00 0x120 0x00 0x124 0x00 0x128 0x00 0x12c 0x30 0x130 0x30 0x134 0x30 0x138 0x30 0x13c 0x30 0x140 0x30 >;
763						phandle = < 0x45 >;
764					};
765
766					cpsw_sleep {
767						pinctrl-single,pins = < 0x110 0x27 0x114 0x27 0x118 0x27 0x11c 0x27 0x120 0x27 0x124 0x27 0x128 0x27 0x12c 0x27 0x130 0x27 0x134 0x27 0x138 0x27 0x13c 0x27 0x140 0x27 >;
768						phandle = < 0x46 >;
769					};
770
771					davinci_mdio_default {
772						pinctrl-single,pins = < 0x148 0x30 0x14c 0x10 >;
773						phandle = < 0x47 >;
774					};
775
776					davinci_mdio_sleep {
777						pinctrl-single,pins = < 0x148 0x27 0x14c 0x27 >;
778						phandle = < 0x48 >;
779					};
780
781					pinmux_mmc1_pins {
782						pinctrl-single,pins = < 0x160 0x2f 0xfc 0x30 0xf8 0x30 0xf4 0x30 0xf0 0x30 0x104 0x30 0x100 0x30 >;
783						phandle = < 0x33 >;
784					};
785
786					pinmux_emmc_pins {
787						pinctrl-single,pins = < 0x80 0x32 0x84 0x32 0x00 0x31 0x04 0x31 0x08 0x31 0x0c 0x31 0x10 0x31 0x14 0x31 0x18 0x31 0x1c 0x31 >;
788						phandle = < 0x36 >;
789					};
790
791					nxp_hdmi_bonelt_pins {
792						pinctrl-single,pins = < 0x1b0 0x03 0xa0 0x08 0xa4 0x08 0xa8 0x08 0xac 0x08 0xb0 0x08 0xb4 0x08 0xb8 0x08 0xbc 0x08 0xc0 0x08 0xc4 0x08 0xc8 0x08 0xcc 0x08 0xd0 0x08 0xd4 0x08 0xd8 0x08 0xdc 0x08 0xe0 0x00 0xe4 0x00 0xe8 0x00 0xec 0x00 >;
793						phandle = < 0x2e >;
794					};
795
796					nxp_hdmi_bonelt_off_pins {
797						pinctrl-single,pins = < 0x1b0 0x03 >;
798						phandle = < 0x2f >;
799					};
800
801					mcasp0_pins {
802						pinctrl-single,pins = < 0x1ac 0x30 0x19c 0x02 0x194 0x10 0x190 0x00 0x6c 0x07 >;
803						phandle = < 0x4b >;
804					};
805				};
806
807				scm_conf@0 {
808					compatible = "syscon\0simple-bus";
809					reg = < 0x00 0x800 >;
810					#address-cells = < 0x01 >;
811					#size-cells = < 0x01 >;
812					ranges = < 0x00 0x00 0x800 >;
813					phandle = < 0x05 >;
814
815					clocks {
816						#address-cells = < 0x01 >;
817						#size-cells = < 0x00 >;
818
819						sys_clkin_ck@40 {
820							#clock-cells = < 0x00 >;
821							compatible = "ti,mux-clock";
822							clocks = < 0x1f 0x20 0x21 0x22 >;
823							ti,bit-shift = < 0x16 >;
824							reg = < 0x40 >;
825							phandle = < 0x08 >;
826						};
827
828						adc_tsc_fck {
829							#clock-cells = < 0x00 >;
830							compatible = "fixed-factor-clock";
831							clocks = < 0x08 >;
832							clock-mult = < 0x01 >;
833							clock-div = < 0x01 >;
834						};
835
836						dcan0_fck {
837							#clock-cells = < 0x00 >;
838							compatible = "fixed-factor-clock";
839							clocks = < 0x08 >;
840							clock-mult = < 0x01 >;
841							clock-div = < 0x01 >;
842							phandle = < 0x37 >;
843						};
844
845						dcan1_fck {
846							#clock-cells = < 0x00 >;
847							compatible = "fixed-factor-clock";
848							clocks = < 0x08 >;
849							clock-mult = < 0x01 >;
850							clock-div = < 0x01 >;
851							phandle = < 0x38 >;
852						};
853
854						mcasp0_fck {
855							#clock-cells = < 0x00 >;
856							compatible = "fixed-factor-clock";
857							clocks = < 0x08 >;
858							clock-mult = < 0x01 >;
859							clock-div = < 0x01 >;
860						};
861
862						mcasp1_fck {
863							#clock-cells = < 0x00 >;
864							compatible = "fixed-factor-clock";
865							clocks = < 0x08 >;
866							clock-mult = < 0x01 >;
867							clock-div = < 0x01 >;
868						};
869
870						smartreflex0_fck {
871							#clock-cells = < 0x00 >;
872							compatible = "fixed-factor-clock";
873							clocks = < 0x08 >;
874							clock-mult = < 0x01 >;
875							clock-div = < 0x01 >;
876						};
877
878						smartreflex1_fck {
879							#clock-cells = < 0x00 >;
880							compatible = "fixed-factor-clock";
881							clocks = < 0x08 >;
882							clock-mult = < 0x01 >;
883							clock-div = < 0x01 >;
884						};
885
886						sha0_fck {
887							#clock-cells = < 0x00 >;
888							compatible = "fixed-factor-clock";
889							clocks = < 0x08 >;
890							clock-mult = < 0x01 >;
891							clock-div = < 0x01 >;
892						};
893
894						aes0_fck {
895							#clock-cells = < 0x00 >;
896							compatible = "fixed-factor-clock";
897							clocks = < 0x08 >;
898							clock-mult = < 0x01 >;
899							clock-div = < 0x01 >;
900						};
901
902						rng_fck {
903							#clock-cells = < 0x00 >;
904							compatible = "fixed-factor-clock";
905							clocks = < 0x08 >;
906							clock-mult = < 0x01 >;
907							clock-div = < 0x01 >;
908						};
909
910						ehrpwm0_tbclk@44e10664 {
911							#clock-cells = < 0x00 >;
912							compatible = "ti,gate-clock";
913							clocks = < 0x23 >;
914							ti,bit-shift = < 0x00 >;
915							reg = < 0x664 >;
916							phandle = < 0x40 >;
917						};
918
919						ehrpwm1_tbclk@44e10664 {
920							#clock-cells = < 0x00 >;
921							compatible = "ti,gate-clock";
922							clocks = < 0x23 >;
923							ti,bit-shift = < 0x01 >;
924							reg = < 0x664 >;
925							phandle = < 0x41 >;
926						};
927
928						ehrpwm2_tbclk@44e10664 {
929							#clock-cells = < 0x00 >;
930							compatible = "ti,gate-clock";
931							clocks = < 0x23 >;
932							ti,bit-shift = < 0x02 >;
933							reg = < 0x664 >;
934							phandle = < 0x42 >;
935						};
936					};
937				};
938
939				wkup_m3_ipc@1324 {
940					compatible = "ti,am3352-wkup-m3-ipc";
941					reg = < 0x1324 0x24 >;
942					interrupts = < 0x4e >;
943					ti,rproc = < 0x24 >;
944					mboxes = < 0x25 0x26 >;
945				};
946
947				dma-router@f90 {
948					compatible = "ti,am335x-edma-crossbar";
949					reg = < 0xf90 0x40 >;
950					#dma-cells = < 0x03 >;
951					dma-requests = < 0x20 >;
952					dma-masters = < 0x27 >;
953					phandle = < 0x32 >;
954				};
955
956				clockdomains {
957				};
958			};
959		};
960
961		interrupt-controller@48200000 {
962			compatible = "ti,am33xx-intc";
963			interrupt-controller;
964			#interrupt-cells = < 0x01 >;
965			reg = < 0x48200000 0x1000 >;
966			phandle = < 0x01 >;
967		};
968
969		edma@49000000 {
970			compatible = "ti,edma3-tpcc";
971			ti,hwmods = "tpcc";
972			reg = < 0x49000000 0x10000 >;
973			reg-names = "edma3_cc";
974			interrupts = < 0x0c 0x0d 0x0e >;
975			interrupt-names = "edma3_ccint\0edma3_mperr\0edma3_ccerrint";
976			dma-requests = < 0x40 >;
977			#dma-cells = < 0x02 >;
978			ti,tptcs = < 0x28 0x07 0x29 0x05 0x2a 0x00 >;
979			ti,edma-memcpy-channels = < 0x14 0x15 >;
980			phandle = < 0x27 >;
981		};
982
983		tptc@49800000 {
984			compatible = "ti,edma3-tptc";
985			ti,hwmods = "tptc0";
986			reg = < 0x49800000 0x100000 >;
987			interrupts = < 0x70 >;
988			interrupt-names = "edma3_tcerrint";
989			phandle = < 0x28 >;
990		};
991
992		tptc@49900000 {
993			compatible = "ti,edma3-tptc";
994			ti,hwmods = "tptc1";
995			reg = < 0x49900000 0x100000 >;
996			interrupts = < 0x71 >;
997			interrupt-names = "edma3_tcerrint";
998			phandle = < 0x29 >;
999		};
1000
1001		tptc@49a00000 {
1002			compatible = "ti,edma3-tptc";
1003			ti,hwmods = "tptc2";
1004			reg = < 0x49a00000 0x100000 >;
1005			interrupts = < 0x72 >;
1006			interrupt-names = "edma3_tcerrint";
1007			phandle = < 0x2a >;
1008		};
1009
1010		gpio@44e07000 {
1011			compatible = "ti,omap4-gpio";
1012			ti,hwmods = "gpio1";
1013			gpio-controller;
1014			#gpio-cells = < 0x02 >;
1015			interrupt-controller;
1016			#interrupt-cells = < 0x02 >;
1017			reg = < 0x44e07000 0x1000 >;
1018			interrupts = < 0x60 >;
1019			phandle = < 0x34 >;
1020		};
1021
1022		gpio@4804c000 {
1023			compatible = "ti,omap4-gpio";
1024			ti,hwmods = "gpio2";
1025			gpio-controller;
1026			#gpio-cells = < 0x02 >;
1027			interrupt-controller;
1028			#interrupt-cells = < 0x02 >;
1029			reg = < 0x4804c000 0x1000 >;
1030			interrupts = < 0x62 >;
1031			phandle = < 0x2d >;
1032		};
1033
1034		gpio@481ac000 {
1035			compatible = "ti,omap4-gpio";
1036			ti,hwmods = "gpio3";
1037			gpio-controller;
1038			#gpio-cells = < 0x02 >;
1039			interrupt-controller;
1040			#interrupt-cells = < 0x02 >;
1041			reg = < 0x481ac000 0x1000 >;
1042			interrupts = < 0x20 >;
1043		};
1044
1045		gpio@481ae000 {
1046			compatible = "ti,omap4-gpio";
1047			ti,hwmods = "gpio4";
1048			gpio-controller;
1049			#gpio-cells = < 0x02 >;
1050			interrupt-controller;
1051			#interrupt-cells = < 0x02 >;
1052			reg = < 0x481ae000 0x1000 >;
1053			interrupts = < 0x3e >;
1054		};
1055
1056		serial@44e09000 {
1057			compatible = "ti,am3352-uart\0ti,omap3-uart";
1058			ti,hwmods = "uart1";
1059			clock-frequency = < 0x2dc6c00 >;
1060			reg = < 0x44e09000 0x2000 >;
1061			interrupts = < 0x48 >;
1062			status = "okay";
1063			dmas = < 0x27 0x1a 0x00 0x27 0x1b 0x00 >;
1064			dma-names = "tx\0rx";
1065			pinctrl-names = "default";
1066			pinctrl-0 = < 0x2b >;
1067		};
1068
1069		serial@48022000 {
1070			compatible = "ti,am3352-uart\0ti,omap3-uart";
1071			ti,hwmods = "uart2";
1072			clock-frequency = < 0x2dc6c00 >;
1073			reg = < 0x48022000 0x2000 >;
1074			interrupts = < 0x49 >;
1075			status = "disabled";
1076			dmas = < 0x27 0x1c 0x00 0x27 0x1d 0x00 >;
1077			dma-names = "tx\0rx";
1078		};
1079
1080		serial@48024000 {
1081			compatible = "ti,am3352-uart\0ti,omap3-uart";
1082			ti,hwmods = "uart3";
1083			clock-frequency = < 0x2dc6c00 >;
1084			reg = < 0x48024000 0x2000 >;
1085			interrupts = < 0x4a >;
1086			status = "disabled";
1087			dmas = < 0x27 0x1e 0x00 0x27 0x1f 0x00 >;
1088			dma-names = "tx\0rx";
1089		};
1090
1091		serial@481a6000 {
1092			compatible = "ti,am3352-uart\0ti,omap3-uart";
1093			ti,hwmods = "uart4";
1094			clock-frequency = < 0x2dc6c00 >;
1095			reg = < 0x481a6000 0x2000 >;
1096			interrupts = < 0x2c >;
1097			status = "disabled";
1098		};
1099
1100		serial@481a8000 {
1101			compatible = "ti,am3352-uart\0ti,omap3-uart";
1102			ti,hwmods = "uart5";
1103			clock-frequency = < 0x2dc6c00 >;
1104			reg = < 0x481a8000 0x2000 >;
1105			interrupts = < 0x2d >;
1106			status = "disabled";
1107		};
1108
1109		serial@481aa000 {
1110			compatible = "ti,am3352-uart\0ti,omap3-uart";
1111			ti,hwmods = "uart6";
1112			clock-frequency = < 0x2dc6c00 >;
1113			reg = < 0x481aa000 0x2000 >;
1114			interrupts = < 0x2e >;
1115			status = "disabled";
1116		};
1117
1118		i2c@44e0b000 {
1119			compatible = "ti,omap4-i2c";
1120			#address-cells = < 0x01 >;
1121			#size-cells = < 0x00 >;
1122			ti,hwmods = "i2c1";
1123			reg = < 0x44e0b000 0x1000 >;
1124			interrupts = < 0x46 >;
1125			status = "okay";
1126			pinctrl-names = "default";
1127			pinctrl-0 = < 0x2c >;
1128			clock-frequency = < 0x61a80 >;
1129
1130			tps@24 {
1131				reg = < 0x24 >;
1132				compatible = "ti,tps65217";
1133				interrupt-controller;
1134				#interrupt-cells = < 0x01 >;
1135				interrupts = < 0x07 >;
1136				interrupt-parent = < 0x01 >;
1137				ti,pmic-shutdown-controller;
1138				phandle = < 0x3e >;
1139
1140				charger {
1141					compatible = "ti,tps65217-charger";
1142					interrupts = < 0x00 0x01 >;
1143					interrupt-names = "USB\0AC";
1144					status = "okay";
1145				};
1146
1147				pwrbutton {
1148					compatible = "ti,tps65217-pwrbutton";
1149					interrupts = < 0x02 >;
1150					status = "okay";
1151				};
1152
1153				regulators {
1154					#address-cells = < 0x01 >;
1155					#size-cells = < 0x00 >;
1156
1157					regulator@0 {
1158						reg = < 0x00 >;
1159						regulator-compatible = "dcdc1";
1160						regulator-name = "vdds_dpr";
1161						regulator-always-on;
1162					};
1163
1164					regulator@1 {
1165						reg = < 0x01 >;
1166						regulator-compatible = "dcdc2";
1167						regulator-name = "vdd_mpu";
1168						regulator-min-microvolt = < 0xe1d48 >;
1169						regulator-max-microvolt = < 0x149f4c >;
1170						regulator-boot-on;
1171						regulator-always-on;
1172						phandle = < 0x04 >;
1173					};
1174
1175					regulator@2 {
1176						reg = < 0x02 >;
1177						regulator-compatible = "dcdc3";
1178						regulator-name = "vdd_core";
1179						regulator-min-microvolt = < 0xe1d48 >;
1180						regulator-max-microvolt = < 0x118c30 >;
1181						regulator-boot-on;
1182						regulator-always-on;
1183					};
1184
1185					regulator@3 {
1186						reg = < 0x03 >;
1187						regulator-compatible = "ldo1";
1188						regulator-name = "vio,vrtc,vdds";
1189						regulator-always-on;
1190					};
1191
1192					regulator@4 {
1193						reg = < 0x04 >;
1194						regulator-compatible = "ldo2";
1195						regulator-name = "vdd_3v3aux";
1196						regulator-always-on;
1197					};
1198
1199					regulator@5 {
1200						reg = < 0x05 >;
1201						regulator-compatible = "ldo3";
1202						regulator-name = "vdd_1v8";
1203						regulator-always-on;
1204						regulator-min-microvolt = < 0x1b7740 >;
1205						regulator-max-microvolt = < 0x1b7740 >;
1206					};
1207
1208					regulator@6 {
1209						reg = < 0x06 >;
1210						regulator-compatible = "ldo4";
1211						regulator-name = "vdd_3v3a";
1212						regulator-always-on;
1213					};
1214				};
1215			};
1216
1217			baseboard_eeprom@50 {
1218				compatible = "atmel,24c256";
1219				reg = < 0x50 >;
1220				#address-cells = < 0x01 >;
1221				#size-cells = < 0x01 >;
1222
1223				baseboard_data@0 {
1224					reg = < 0x00 0x100 >;
1225				};
1226			};
1227
1228			tda19988@70 {
1229				compatible = "nxp,tda998x";
1230				reg = < 0x70 >;
1231				nxp,calib-gpios = < 0x2d 0x19 0x00 >;
1232				interrupts-extended = < 0x2d 0x19 0x08 >;
1233				pinctrl-names = "default\0off";
1234				pinctrl-0 = < 0x2e >;
1235				pinctrl-1 = < 0x2f >;
1236				#sound-dai-cells = < 0x00 >;
1237				audio-ports = < 0x02 0x03 >;
1238				phandle = < 0x51 >;
1239
1240				ports {
1241
1242					port@0 {
1243
1244						endpoint@0 {
1245							remote-endpoint = < 0x30 >;
1246							phandle = < 0x4a >;
1247						};
1248					};
1249				};
1250			};
1251		};
1252
1253		i2c@4802a000 {
1254			compatible = "ti,omap4-i2c";
1255			#address-cells = < 0x01 >;
1256			#size-cells = < 0x00 >;
1257			ti,hwmods = "i2c2";
1258			reg = < 0x4802a000 0x1000 >;
1259			interrupts = < 0x47 >;
1260			status = "disabled";
1261		};
1262
1263		i2c@4819c000 {
1264			compatible = "ti,omap4-i2c";
1265			#address-cells = < 0x01 >;
1266			#size-cells = < 0x00 >;
1267			ti,hwmods = "i2c3";
1268			reg = < 0x4819c000 0x1000 >;
1269			interrupts = < 0x1e >;
1270			status = "okay";
1271			pinctrl-names = "default";
1272			pinctrl-0 = < 0x31 >;
1273			clock-frequency = < 0x186a0 >;
1274
1275			cape_eeprom0@54 {
1276				compatible = "atmel,24c256";
1277				reg = < 0x54 >;
1278				#address-cells = < 0x01 >;
1279				#size-cells = < 0x01 >;
1280
1281				cape_data@0 {
1282					reg = < 0x00 0x100 >;
1283				};
1284			};
1285
1286			cape_eeprom1@55 {
1287				compatible = "atmel,24c256";
1288				reg = < 0x55 >;
1289				#address-cells = < 0x01 >;
1290				#size-cells = < 0x01 >;
1291
1292				cape_data@0 {
1293					reg = < 0x00 0x100 >;
1294				};
1295			};
1296
1297			cape_eeprom2@56 {
1298				compatible = "atmel,24c256";
1299				reg = < 0x56 >;
1300				#address-cells = < 0x01 >;
1301				#size-cells = < 0x01 >;
1302
1303				cape_data@0 {
1304					reg = < 0x00 0x100 >;
1305				};
1306			};
1307
1308			cape_eeprom3@57 {
1309				compatible = "atmel,24c256";
1310				reg = < 0x57 >;
1311				#address-cells = < 0x01 >;
1312				#size-cells = < 0x01 >;
1313
1314				cape_data@0 {
1315					reg = < 0x00 0x100 >;
1316				};
1317			};
1318		};
1319
1320		mmc@48060000 {
1321			compatible = "ti,omap4-hsmmc";
1322			ti,hwmods = "mmc1";
1323			ti,dual-volt;
1324			ti,needs-special-reset;
1325			ti,needs-special-hs-handling;
1326			dmas = < 0x32 0x18 0x00 0x00 0x32 0x19 0x00 0x00 >;
1327			dma-names = "tx\0rx";
1328			interrupts = < 0x40 >;
1329			reg = < 0x48060000 0x1000 >;
1330			status = "okay";
1331			bus-width = < 0x04 >;
1332			pinctrl-names = "default";
1333			pinctrl-0 = < 0x33 >;
1334			cd-gpios = < 0x34 0x06 0x01 >;
1335			vmmc-supply = < 0x35 >;
1336		};
1337
1338		mmc@481d8000 {
1339			compatible = "ti,omap4-hsmmc";
1340			ti,hwmods = "mmc2";
1341			ti,needs-special-reset;
1342			dmas = < 0x27 0x02 0x00 0x27 0x03 0x00 >;
1343			dma-names = "tx\0rx";
1344			interrupts = < 0x1c >;
1345			reg = < 0x481d8000 0x1000 >;
1346			status = "okay";
1347			vmmc-supply = < 0x35 >;
1348			pinctrl-names = "default";
1349			pinctrl-0 = < 0x36 >;
1350			bus-width = < 0x08 >;
1351		};
1352
1353		mmc@47810000 {
1354			compatible = "ti,omap4-hsmmc";
1355			ti,hwmods = "mmc3";
1356			ti,needs-special-reset;
1357			interrupts = < 0x1d >;
1358			reg = < 0x47810000 0x1000 >;
1359			status = "disabled";
1360		};
1361
1362		spinlock@480ca000 {
1363			compatible = "ti,omap4-hwspinlock";
1364			reg = < 0x480ca000 0x1000 >;
1365			ti,hwmods = "spinlock";
1366			#hwlock-cells = < 0x01 >;
1367		};
1368
1369		wdt@44e35000 {
1370			compatible = "ti,omap3-wdt";
1371			ti,hwmods = "wd_timer2";
1372			reg = < 0x44e35000 0x1000 >;
1373			interrupts = < 0x5b >;
1374		};
1375
1376		can@481cc000 {
1377			compatible = "ti,am3352-d_can";
1378			ti,hwmods = "d_can0";
1379			reg = < 0x481cc000 0x2000 >;
1380			clocks = < 0x37 >;
1381			clock-names = "fck";
1382			syscon-raminit = < 0x05 0x644 0x00 >;
1383			interrupts = < 0x34 >;
1384			status = "disabled";
1385		};
1386
1387		can@481d0000 {
1388			compatible = "ti,am3352-d_can";
1389			ti,hwmods = "d_can1";
1390			reg = < 0x481d0000 0x2000 >;
1391			clocks = < 0x38 >;
1392			clock-names = "fck";
1393			syscon-raminit = < 0x05 0x644 0x01 >;
1394			interrupts = < 0x37 >;
1395			status = "disabled";
1396		};
1397
1398		mailbox@480c8000 {
1399			compatible = "ti,omap4-mailbox";
1400			reg = < 0x480c8000 0x200 >;
1401			interrupts = < 0x4d >;
1402			ti,hwmods = "mailbox";
1403			#mbox-cells = < 0x01 >;
1404			ti,mbox-num-users = < 0x04 >;
1405			ti,mbox-num-fifos = < 0x08 >;
1406			phandle = < 0x25 >;
1407
1408			wkup_m3 {
1409				ti,mbox-send-noirq;
1410				ti,mbox-tx = < 0x00 0x00 0x00 >;
1411				ti,mbox-rx = < 0x00 0x00 0x03 >;
1412				phandle = < 0x26 >;
1413			};
1414		};
1415
1416		timer@44e31000 {
1417			compatible = "ti,am335x-timer-1ms";
1418			reg = < 0x44e31000 0x400 >;
1419			interrupts = < 0x43 >;
1420			ti,hwmods = "timer1";
1421			ti,timer-alwon;
1422			clocks = < 0x39 >;
1423			clock-names = "fck";
1424		};
1425
1426		timer@48040000 {
1427			compatible = "ti,am335x-timer";
1428			reg = < 0x48040000 0x400 >;
1429			interrupts = < 0x44 >;
1430			ti,hwmods = "timer2";
1431			clocks = < 0x3a >;
1432			clock-names = "fck";
1433		};
1434
1435		timer@48042000 {
1436			compatible = "ti,am335x-timer";
1437			reg = < 0x48042000 0x400 >;
1438			interrupts = < 0x45 >;
1439			ti,hwmods = "timer3";
1440		};
1441
1442		timer@48044000 {
1443			compatible = "ti,am335x-timer";
1444			reg = < 0x48044000 0x400 >;
1445			interrupts = < 0x5c >;
1446			ti,hwmods = "timer4";
1447			ti,timer-pwm;
1448		};
1449
1450		timer@48046000 {
1451			compatible = "ti,am335x-timer";
1452			reg = < 0x48046000 0x400 >;
1453			interrupts = < 0x5d >;
1454			ti,hwmods = "timer5";
1455			ti,timer-pwm;
1456		};
1457
1458		timer@48048000 {
1459			compatible = "ti,am335x-timer";
1460			reg = < 0x48048000 0x400 >;
1461			interrupts = < 0x5e >;
1462			ti,hwmods = "timer6";
1463			ti,timer-pwm;
1464		};
1465
1466		timer@4804a000 {
1467			compatible = "ti,am335x-timer";
1468			reg = < 0x4804a000 0x400 >;
1469			interrupts = < 0x5f >;
1470			ti,hwmods = "timer7";
1471			ti,timer-pwm;
1472		};
1473
1474		rtc@44e3e000 {
1475			compatible = "ti,am3352-rtc\0ti,da830-rtc";
1476			reg = < 0x44e3e000 0x1000 >;
1477			interrupts = < 0x4b 0x4c >;
1478			ti,hwmods = "rtc";
1479			clocks = < 0x17 0x14 0x138 0x00 >;
1480			clock-names = "ext-clk\0int-clk";
1481			system-power-controller;
1482		};
1483
1484		spi@48030000 {
1485			compatible = "ti,omap4-mcspi";
1486			#address-cells = < 0x01 >;
1487			#size-cells = < 0x00 >;
1488			reg = < 0x48030000 0x400 >;
1489			interrupts = < 0x41 >;
1490			ti,spi-num-cs = < 0x02 >;
1491			ti,hwmods = "spi0";
1492			dmas = < 0x27 0x10 0x00 0x27 0x11 0x00 0x27 0x12 0x00 0x27 0x13 0x00 >;
1493			dma-names = "tx0\0rx0\0tx1\0rx1";
1494			status = "disabled";
1495		};
1496
1497		spi@481a0000 {
1498			compatible = "ti,omap4-mcspi";
1499			#address-cells = < 0x01 >;
1500			#size-cells = < 0x00 >;
1501			reg = < 0x481a0000 0x400 >;
1502			interrupts = < 0x7d >;
1503			ti,spi-num-cs = < 0x02 >;
1504			ti,hwmods = "spi1";
1505			dmas = < 0x27 0x2a 0x00 0x27 0x2b 0x00 0x27 0x2c 0x00 0x27 0x2d 0x00 >;
1506			dma-names = "tx0\0rx0\0tx1\0rx1";
1507			status = "disabled";
1508		};
1509
1510		usb@47400000 {
1511			compatible = "ti,am33xx-usb";
1512			reg = < 0x47400000 0x1000 >;
1513			ranges;
1514			#address-cells = < 0x01 >;
1515			#size-cells = < 0x01 >;
1516			ti,hwmods = "usb_otg_hs";
1517			status = "okay";
1518
1519			control@44e10620 {
1520				compatible = "ti,am335x-usb-ctrl-module";
1521				reg = < 0x44e10620 0x10 0x44e10648 0x04 >;
1522				reg-names = "phy_ctrl\0wakeup";
1523				status = "okay";
1524				phandle = < 0x3b >;
1525			};
1526
1527			usb-phy@47401300 {
1528				compatible = "ti,am335x-usb-phy";
1529				reg = < 0x47401300 0x100 >;
1530				reg-names = "phy";
1531				status = "okay";
1532				ti,ctrl_mod = < 0x3b >;
1533				#phy-cells = < 0x00 >;
1534				phandle = < 0x3c >;
1535			};
1536
1537			usb@47401000 {
1538				compatible = "ti,musb-am33xx";
1539				status = "okay";
1540				reg = < 0x47401400 0x400 0x47401000 0x200 >;
1541				reg-names = "mc\0control";
1542				interrupts = < 0x12 >;
1543				interrupt-names = "mc\0vbus";
1544				dr_mode = "peripheral";
1545				mentor,multipoint = < 0x01 >;
1546				mentor,num-eps = < 0x10 >;
1547				mentor,ram-bits = < 0x0c >;
1548				mentor,power = < 0x1f4 >;
1549				phys = < 0x3c >;
1550				dmas = < 0x3d 0x00 0x00 0x3d 0x01 0x00 0x3d 0x02 0x00 0x3d 0x03 0x00 0x3d 0x04 0x00 0x3d 0x05 0x00 0x3d 0x06 0x00 0x3d 0x07 0x00 0x3d 0x08 0x00 0x3d 0x09 0x00 0x3d 0x0a 0x00 0x3d 0x0b 0x00 0x3d 0x0c 0x00 0x3d 0x0d 0x00 0x3d 0x0e 0x00 0x3d 0x00 0x01 0x3d 0x01 0x01 0x3d 0x02 0x01 0x3d 0x03 0x01 0x3d 0x04 0x01 0x3d 0x05 0x01 0x3d 0x06 0x01 0x3d 0x07 0x01 0x3d 0x08 0x01 0x3d 0x09 0x01 0x3d 0x0a 0x01 0x3d 0x0b 0x01 0x3d 0x0c 0x01 0x3d 0x0d 0x01 0x3d 0x0e 0x01 >;
1551				dma-names = "rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0tx8\0tx9\0tx10\0tx11\0tx12\0tx13\0tx14\0tx15";
1552				interrupts-extended = < 0x01 0x12 0x3e 0x00 >;
1553			};
1554
1555			usb-phy@47401b00 {
1556				compatible = "ti,am335x-usb-phy";
1557				reg = < 0x47401b00 0x100 >;
1558				reg-names = "phy";
1559				status = "okay";
1560				ti,ctrl_mod = < 0x3b >;
1561				#phy-cells = < 0x00 >;
1562				phandle = < 0x3f >;
1563			};
1564
1565			usb@47401800 {
1566				compatible = "ti,musb-am33xx";
1567				status = "okay";
1568				reg = < 0x47401c00 0x400 0x47401800 0x200 >;
1569				reg-names = "mc\0control";
1570				interrupts = < 0x13 >;
1571				interrupt-names = "mc";
1572				dr_mode = "host";
1573				mentor,multipoint = < 0x01 >;
1574				mentor,num-eps = < 0x10 >;
1575				mentor,ram-bits = < 0x0c >;
1576				mentor,power = < 0x1f4 >;
1577				phys = < 0x3f >;
1578				dmas = < 0x3d 0x0f 0x00 0x3d 0x10 0x00 0x3d 0x11 0x00 0x3d 0x12 0x00 0x3d 0x13 0x00 0x3d 0x14 0x00 0x3d 0x15 0x00 0x3d 0x16 0x00 0x3d 0x17 0x00 0x3d 0x18 0x00 0x3d 0x19 0x00 0x3d 0x1a 0x00 0x3d 0x1b 0x00 0x3d 0x1c 0x00 0x3d 0x1d 0x00 0x3d 0x0f 0x01 0x3d 0x10 0x01 0x3d 0x11 0x01 0x3d 0x12 0x01 0x3d 0x13 0x01 0x3d 0x14 0x01 0x3d 0x15 0x01 0x3d 0x16 0x01 0x3d 0x17 0x01 0x3d 0x18 0x01 0x3d 0x19 0x01 0x3d 0x1a 0x01 0x3d 0x1b 0x01 0x3d 0x1c 0x01 0x3d 0x1d 0x01 >;
1579				dma-names = "rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0tx8\0tx9\0tx10\0tx11\0tx12\0tx13\0tx14\0tx15";
1580			};
1581
1582			dma-controller@47402000 {
1583				compatible = "ti,am3359-cppi41";
1584				reg = < 0x47400000 0x1000 0x47402000 0x1000 0x47403000 0x1000 0x47404000 0x4000 >;
1585				reg-names = "glue\0controller\0scheduler\0queuemgr";
1586				interrupts = < 0x11 >;
1587				interrupt-names = "glue";
1588				#dma-cells = < 0x02 >;
1589				#dma-channels = < 0x1e >;
1590				#dma-requests = < 0x100 >;
1591				status = "okay";
1592				phandle = < 0x3d >;
1593			};
1594		};
1595
1596		epwmss@48300000 {
1597			compatible = "ti,am33xx-pwmss";
1598			reg = < 0x48300000 0x10 >;
1599			ti,hwmods = "epwmss0";
1600			#address-cells = < 0x01 >;
1601			#size-cells = < 0x01 >;
1602			status = "disabled";
1603			ranges = < 0x48300100 0x48300100 0x80 0x48300180 0x48300180 0x80 0x48300200 0x48300200 0x80 >;
1604
1605			ecap@48300100 {
1606				compatible = "ti,am3352-ecap\0ti,am33xx-ecap";
1607				#pwm-cells = < 0x03 >;
1608				reg = < 0x48300100 0x80 >;
1609				clocks = < 0x23 >;
1610				clock-names = "fck";
1611				interrupts = < 0x1f >;
1612				interrupt-names = "ecap0";
1613				status = "disabled";
1614			};
1615
1616			pwm@48300200 {
1617				compatible = "ti,am3352-ehrpwm\0ti,am33xx-ehrpwm";
1618				#pwm-cells = < 0x03 >;
1619				reg = < 0x48300200 0x80 >;
1620				clocks = < 0x40 0x23 >;
1621				clock-names = "tbclk\0fck";
1622				status = "disabled";
1623			};
1624		};
1625
1626		epwmss@48302000 {
1627			compatible = "ti,am33xx-pwmss";
1628			reg = < 0x48302000 0x10 >;
1629			ti,hwmods = "epwmss1";
1630			#address-cells = < 0x01 >;
1631			#size-cells = < 0x01 >;
1632			status = "disabled";
1633			ranges = < 0x48302100 0x48302100 0x80 0x48302180 0x48302180 0x80 0x48302200 0x48302200 0x80 >;
1634
1635			ecap@48302100 {
1636				compatible = "ti,am3352-ecap\0ti,am33xx-ecap";
1637				#pwm-cells = < 0x03 >;
1638				reg = < 0x48302100 0x80 >;
1639				clocks = < 0x23 >;
1640				clock-names = "fck";
1641				interrupts = < 0x2f >;
1642				interrupt-names = "ecap1";
1643				status = "disabled";
1644			};
1645
1646			pwm@48302200 {
1647				compatible = "ti,am3352-ehrpwm\0ti,am33xx-ehrpwm";
1648				#pwm-cells = < 0x03 >;
1649				reg = < 0x48302200 0x80 >;
1650				clocks = < 0x41 0x23 >;
1651				clock-names = "tbclk\0fck";
1652				status = "disabled";
1653			};
1654		};
1655
1656		epwmss@48304000 {
1657			compatible = "ti,am33xx-pwmss";
1658			reg = < 0x48304000 0x10 >;
1659			ti,hwmods = "epwmss2";
1660			#address-cells = < 0x01 >;
1661			#size-cells = < 0x01 >;
1662			status = "disabled";
1663			ranges = < 0x48304100 0x48304100 0x80 0x48304180 0x48304180 0x80 0x48304200 0x48304200 0x80 >;
1664
1665			ecap@48304100 {
1666				compatible = "ti,am3352-ecap\0ti,am33xx-ecap";
1667				#pwm-cells = < 0x03 >;
1668				reg = < 0x48304100 0x80 >;
1669				clocks = < 0x23 >;
1670				clock-names = "fck";
1671				interrupts = < 0x3d >;
1672				interrupt-names = "ecap2";
1673				status = "disabled";
1674			};
1675
1676			pwm@48304200 {
1677				compatible = "ti,am3352-ehrpwm\0ti,am33xx-ehrpwm";
1678				#pwm-cells = < 0x03 >;
1679				reg = < 0x48304200 0x80 >;
1680				clocks = < 0x42 0x23 >;
1681				clock-names = "tbclk\0fck";
1682				status = "disabled";
1683			};
1684		};
1685
1686		ethernet@4a100000 {
1687			compatible = "ti,am335x-cpsw\0ti,cpsw";
1688			ti,hwmods = "cpgmac0";
1689			clocks = < 0x43 0x44 >;
1690			clock-names = "fck\0cpts";
1691			cpdma_channels = < 0x08 >;
1692			ale_entries = < 0x400 >;
1693			bd_ram_size = < 0x2000 >;
1694			mac_control = < 0x20 >;
1695			slaves = < 0x01 >;
1696			active_slave = < 0x00 >;
1697			cpts_clock_mult = < 0x80000000 >;
1698			cpts_clock_shift = < 0x1d >;
1699			reg = < 0x4a100000 0x800 0x4a101200 0x100 >;
1700			#address-cells = < 0x01 >;
1701			#size-cells = < 0x01 >;
1702			interrupts = < 0x28 0x29 0x2a 0x2b >;
1703			ranges;
1704			syscon = < 0x05 >;
1705			status = "okay";
1706			pinctrl-names = "default\0sleep";
1707			pinctrl-0 = < 0x45 >;
1708			pinctrl-1 = < 0x46 >;
1709
1710			mdio@4a101000 {
1711				compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
1712				#address-cells = < 0x01 >;
1713				#size-cells = < 0x00 >;
1714				ti,hwmods = "davinci_mdio";
1715				bus_freq = < 0xf4240 >;
1716				reg = < 0x4a101000 0x100 >;
1717				status = "okay";
1718				pinctrl-names = "default\0sleep";
1719				pinctrl-0 = < 0x47 >;
1720				pinctrl-1 = < 0x48 >;
1721
1722				ethernet-phy@0 {
1723					reg = < 0x00 >;
1724					phandle = < 0x49 >;
1725				};
1726			};
1727
1728			slave@4a100200 {
1729				mac-address = [ 00 00 00 00 00 00 ];
1730				phy-handle = < 0x49 >;
1731				phy-mode = "mii";
1732			};
1733
1734			slave@4a100300 {
1735				mac-address = [ 00 00 00 00 00 00 ];
1736			};
1737
1738			cpsw-phy-sel@44e10650 {
1739				compatible = "ti,am3352-cpsw-phy-sel";
1740				reg = < 0x44e10650 0x04 >;
1741				reg-names = "gmii-sel";
1742			};
1743		};
1744
1745		ocmcram@40300000 {
1746			compatible = "mmio-sram";
1747			reg = < 0x40300000 0x10000 >;
1748			ranges = < 0x00 0x40300000 0x10000 >;
1749			#address-cells = < 0x01 >;
1750			#size-cells = < 0x01 >;
1751
1752			pm-sram-code@0 {
1753				compatible = "ti,sram";
1754				reg = < 0x00 0x1000 >;
1755				protect-exec;
1756				phandle = < 0x06 >;
1757			};
1758
1759			pm-sram-data@1000 {
1760				compatible = "ti,sram";
1761				reg = < 0x1000 0x1000 >;
1762				pool;
1763				phandle = < 0x07 >;
1764			};
1765		};
1766
1767		elm@48080000 {
1768			compatible = "ti,am3352-elm";
1769			reg = < 0x48080000 0x2000 >;
1770			interrupts = < 0x04 >;
1771			ti,hwmods = "elm";
1772			status = "disabled";
1773		};
1774
1775		lcdc@4830e000 {
1776			compatible = "ti,am33xx-tilcdc";
1777			reg = < 0x4830e000 0x1000 >;
1778			interrupts = < 0x24 >;
1779			ti,hwmods = "lcdc";
1780			status = "okay";
1781			blue-and-red-wiring = "straight";
1782
1783			port {
1784
1785				endpoint@0 {
1786					remote-endpoint = < 0x4a >;
1787					phandle = < 0x30 >;
1788				};
1789			};
1790		};
1791
1792		tscadc@44e0d000 {
1793			compatible = "ti,am3359-tscadc";
1794			reg = < 0x44e0d000 0x1000 >;
1795			interrupts = < 0x10 >;
1796			ti,hwmods = "adc_tsc";
1797			status = "disabled";
1798			dmas = < 0x27 0x35 0x00 0x27 0x39 0x00 >;
1799			dma-names = "fifo0\0fifo1";
1800
1801			tsc {
1802				compatible = "ti,am3359-tsc";
1803			};
1804
1805			adc {
1806				#io-channel-cells = < 0x01 >;
1807				compatible = "ti,am3359-adc";
1808			};
1809		};
1810
1811		emif@4c000000 {
1812			compatible = "ti,emif-am3352";
1813			reg = < 0x4c000000 0x1000000 >;
1814			ti,hwmods = "emif";
1815			interrupts = < 0x65 >;
1816			sram = < 0x06 0x07 >;
1817			ti,no-idle;
1818		};
1819
1820		gpmc@50000000 {
1821			compatible = "ti,am3352-gpmc";
1822			ti,hwmods = "gpmc";
1823			ti,no-idle-on-init;
1824			reg = < 0x50000000 0x2000 >;
1825			interrupts = < 0x64 >;
1826			dmas = < 0x27 0x34 0x00 >;
1827			dma-names = "rxtx";
1828			gpmc,num-cs = < 0x07 >;
1829			gpmc,num-waitpins = < 0x02 >;
1830			#address-cells = < 0x02 >;
1831			#size-cells = < 0x01 >;
1832			interrupt-controller;
1833			#interrupt-cells = < 0x02 >;
1834			gpio-controller;
1835			#gpio-cells = < 0x02 >;
1836			status = "disabled";
1837		};
1838
1839		sham@53100000 {
1840			compatible = "ti,omap4-sham";
1841			ti,hwmods = "sham";
1842			reg = < 0x53100000 0x200 >;
1843			interrupts = < 0x6d >;
1844			dmas = < 0x27 0x24 0x00 >;
1845			dma-names = "rx";
1846			status = "okay";
1847		};
1848
1849		aes@53500000 {
1850			compatible = "ti,omap4-aes";
1851			ti,hwmods = "aes";
1852			reg = < 0x53500000 0xa0 >;
1853			interrupts = < 0x67 >;
1854			dmas = < 0x27 0x06 0x00 0x27 0x05 0x00 >;
1855			dma-names = "tx\0rx";
1856			status = "okay";
1857		};
1858
1859		mcasp@48038000 {
1860			compatible = "ti,am33xx-mcasp-audio";
1861			ti,hwmods = "mcasp0";
1862			reg = < 0x48038000 0x2000 0x46000000 0x400000 >;
1863			reg-names = "mpu\0dat";
1864			interrupts = < 0x50 0x51 >;
1865			interrupt-names = "tx\0rx";
1866			status = "okay";
1867			dmas = < 0x27 0x08 0x02 0x27 0x09 0x02 >;
1868			dma-names = "tx\0rx";
1869			#sound-dai-cells = < 0x00 >;
1870			pinctrl-names = "default";
1871			pinctrl-0 = < 0x4b >;
1872			op-mode = < 0x00 >;
1873			tdm-slots = < 0x02 >;
1874			serial-dir = < 0x00 0x00 0x01 0x00 >;
1875			tx-num-evt = < 0x20 >;
1876			rx-num-evt = < 0x20 >;
1877			phandle = < 0x4f >;
1878		};
1879
1880		mcasp@4803c000 {
1881			compatible = "ti,am33xx-mcasp-audio";
1882			ti,hwmods = "mcasp1";
1883			reg = < 0x4803c000 0x2000 0x46400000 0x400000 >;
1884			reg-names = "mpu\0dat";
1885			interrupts = < 0x52 0x53 >;
1886			interrupt-names = "tx\0rx";
1887			status = "disabled";
1888			dmas = < 0x27 0x0a 0x02 0x27 0x0b 0x02 >;
1889			dma-names = "tx\0rx";
1890		};
1891
1892		rng@48310000 {
1893			compatible = "ti,omap4-rng";
1894			ti,hwmods = "rng";
1895			reg = < 0x48310000 0x2000 >;
1896			interrupts = < 0x6f >;
1897		};
1898	};
1899
1900	memory@80000000 {
1901		device_type = "memory";
1902		reg = < 0x80000000 0x10000000 >;
1903	};
1904
1905	leds {
1906		pinctrl-names = "default";
1907		pinctrl-0 = < 0x4c >;
1908		compatible = "gpio-leds";
1909
1910		led2 {
1911			label = "beaglebone:green:heartbeat";
1912			gpios = < 0x2d 0x15 0x00 >;
1913			linux,default-trigger = "heartbeat";
1914			default-state = "off";
1915		};
1916
1917		led3 {
1918			label = "beaglebone:green:mmc0";
1919			gpios = < 0x2d 0x16 0x00 >;
1920			linux,default-trigger = "mmc0";
1921			default-state = "off";
1922		};
1923
1924		led4 {
1925			label = "beaglebone:green:usr2";
1926			gpios = < 0x2d 0x17 0x00 >;
1927			linux,default-trigger = "cpu0";
1928			default-state = "off";
1929		};
1930
1931		led5 {
1932			label = "beaglebone:green:usr3";
1933			gpios = < 0x2d 0x18 0x00 >;
1934			linux,default-trigger = "mmc1";
1935			default-state = "off";
1936		};
1937	};
1938
1939	fixedregulator0 {
1940		compatible = "regulator-fixed";
1941		regulator-name = "vmmcsd_fixed";
1942		regulator-min-microvolt = < 0x325aa0 >;
1943		regulator-max-microvolt = < 0x325aa0 >;
1944		phandle = < 0x35 >;
1945	};
1946
1947	clk_mcasp0_fixed {
1948		#clock-cells = < 0x00 >;
1949		compatible = "fixed-clock";
1950		clock-frequency = < 0x1770000 >;
1951		phandle = < 0x4d >;
1952	};
1953
1954	clk_mcasp0 {
1955		#clock-cells = < 0x00 >;
1956		compatible = "gpio-gate-clock";
1957		clocks = < 0x4d >;
1958		enable-gpios = < 0x2d 0x1b 0x00 >;
1959		phandle = < 0x50 >;
1960	};
1961
1962	sound {
1963		compatible = "simple-audio-card";
1964		simple-audio-card,name = "TI BeagleBone Black";
1965		simple-audio-card,format = "i2s";
1966		simple-audio-card,bitclock-master = < 0x4e >;
1967		simple-audio-card,frame-master = < 0x4e >;
1968
1969		simple-audio-card,cpu {
1970			sound-dai = < 0x4f >;
1971			clocks = < 0x50 >;
1972			phandle = < 0x4e >;
1973		};
1974
1975		simple-audio-card,codec {
1976			sound-dai = < 0x51 >;
1977		};
1978	};
1979};
1980