1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = < 0x01 >;
15	#size-cells = < 0x01 >;
16	model = "Qualcomm APQ8064/IFC6410";
17	compatible = "qcom,apq8064-ifc6410\0qcom,apq8064";
18	interrupt-parent = < 0x01 >;
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	aliases {
25		serial0 = "/soc/gsbi@16600000/serial@16640000";
26		serial1 = "/soc/gsbi@16500000/serial@16540000";
27		i2c0 = "/soc/gsbi@12440000/i2c@12460000";
28		i2c1 = "/soc/gsbi@12480000/i2c@124a0000";
29		i2c2 = "/soc/gsbi@16200000/i2c@16280000";
30		i2c3 = "/soc/gsbi@16300000/i2c@16380000";
31		spi0 = "/soc/gsbi@1a200000/spi@1a280000";
32	};
33
34	memory {
35		device_type = "memory";
36		reg = < 0x00 0x00 >;
37	};
38
39	reserved-memory {
40		#address-cells = < 0x01 >;
41		#size-cells = < 0x01 >;
42		ranges;
43
44		smem@80000000 {
45			reg = < 0x80000000 0x200000 >;
46			no-map;
47			phandle = < 0x0e >;
48		};
49
50		wcnss@8f000000 {
51			reg = < 0x8f000000 0x700000 >;
52			no-map;
53			phandle = < 0x55 >;
54		};
55	};
56
57	cpus {
58		#address-cells = < 0x01 >;
59		#size-cells = < 0x00 >;
60
61		cpu@0 {
62			compatible = "qcom,krait";
63			enable-method = "qcom,kpss-acc-v1";
64			device_type = "cpu";
65			reg = < 0x00 >;
66			next-level-cache = < 0x02 >;
67			qcom,acc = < 0x03 >;
68			qcom,saw = < 0x04 >;
69			cpu-idle-states = < 0x05 >;
70			phandle = < 0x66 >;
71		};
72
73		cpu@1 {
74			compatible = "qcom,krait";
75			enable-method = "qcom,kpss-acc-v1";
76			device_type = "cpu";
77			reg = < 0x01 >;
78			next-level-cache = < 0x02 >;
79			qcom,acc = < 0x06 >;
80			qcom,saw = < 0x07 >;
81			cpu-idle-states = < 0x05 >;
82			phandle = < 0x68 >;
83		};
84
85		cpu@2 {
86			compatible = "qcom,krait";
87			enable-method = "qcom,kpss-acc-v1";
88			device_type = "cpu";
89			reg = < 0x02 >;
90			next-level-cache = < 0x02 >;
91			qcom,acc = < 0x08 >;
92			qcom,saw = < 0x09 >;
93			cpu-idle-states = < 0x05 >;
94			phandle = < 0x6a >;
95		};
96
97		cpu@3 {
98			compatible = "qcom,krait";
99			enable-method = "qcom,kpss-acc-v1";
100			device_type = "cpu";
101			reg = < 0x03 >;
102			next-level-cache = < 0x02 >;
103			qcom,acc = < 0x0a >;
104			qcom,saw = < 0x0b >;
105			cpu-idle-states = < 0x05 >;
106			phandle = < 0x6c >;
107		};
108
109		l2-cache {
110			compatible = "cache";
111			cache-level = < 0x02 >;
112			phandle = < 0x02 >;
113		};
114
115		idle-states {
116
117			spc {
118				compatible = "qcom,idle-state-spc\0arm,idle-state";
119				entry-latency-us = < 0x190 >;
120				exit-latency-us = < 0x384 >;
121				min-residency-us = < 0xbb8 >;
122				phandle = < 0x05 >;
123			};
124		};
125	};
126
127	thermal-zones {
128
129		cpu-thermal0 {
130			polling-delay-passive = < 0xfa >;
131			polling-delay = < 0x3e8 >;
132			thermal-sensors = < 0x0c 0x07 >;
133			coefficients = < 0x4af 0x00 >;
134
135			trips {
136
137				trip0 {
138					temperature = < 0x124f8 >;
139					hysteresis = < 0x7d0 >;
140					type = "passive";
141				};
142
143				trip1 {
144					temperature = < 0x1adb0 >;
145					hysteresis = < 0x7d0 >;
146					type = "critical";
147				};
148			};
149		};
150
151		cpu-thermal1 {
152			polling-delay-passive = < 0xfa >;
153			polling-delay = < 0x3e8 >;
154			thermal-sensors = < 0x0c 0x08 >;
155			coefficients = < 0x46c 0x00 >;
156
157			trips {
158
159				trip0 {
160					temperature = < 0x124f8 >;
161					hysteresis = < 0x7d0 >;
162					type = "passive";
163				};
164
165				trip1 {
166					temperature = < 0x1adb0 >;
167					hysteresis = < 0x7d0 >;
168					type = "critical";
169				};
170			};
171		};
172
173		cpu-thermal2 {
174			polling-delay-passive = < 0xfa >;
175			polling-delay = < 0x3e8 >;
176			thermal-sensors = < 0x0c 0x09 >;
177			coefficients = < 0x4af 0x00 >;
178
179			trips {
180
181				trip0 {
182					temperature = < 0x124f8 >;
183					hysteresis = < 0x7d0 >;
184					type = "passive";
185				};
186
187				trip1 {
188					temperature = < 0x1adb0 >;
189					hysteresis = < 0x7d0 >;
190					type = "critical";
191				};
192			};
193		};
194
195		cpu-thermal3 {
196			polling-delay-passive = < 0xfa >;
197			polling-delay = < 0x3e8 >;
198			thermal-sensors = < 0x0c 0x0a >;
199			coefficients = < 0x46c 0x00 >;
200
201			trips {
202
203				trip0 {
204					temperature = < 0x124f8 >;
205					hysteresis = < 0x7d0 >;
206					type = "passive";
207				};
208
209				trip1 {
210					temperature = < 0x1adb0 >;
211					hysteresis = < 0x7d0 >;
212					type = "critical";
213				};
214			};
215		};
216	};
217
218	cpu-pmu {
219		compatible = "qcom,krait-pmu";
220		interrupts = < 0x01 0x0a 0x304 >;
221	};
222
223	clocks {
224
225		cxo_board {
226			compatible = "fixed-clock";
227			#clock-cells = < 0x00 >;
228			clock-frequency = < 0x124f800 >;
229			phandle = < 0x2f >;
230		};
231
232		pxo_board {
233			compatible = "fixed-clock";
234			#clock-cells = < 0x00 >;
235			clock-frequency = < 0x19bfcc0 >;
236		};
237
238		sleep_clk {
239			compatible = "fixed-clock";
240			#clock-cells = < 0x00 >;
241			clock-frequency = < 0x8000 >;
242			phandle = < 0x2e >;
243		};
244	};
245
246	hwmutex {
247		compatible = "qcom,sfpb-mutex";
248		syscon = < 0x0d 0x604 0x04 >;
249		#hwlock-cells = < 0x01 >;
250		phandle = < 0x0f >;
251	};
252
253	smem {
254		compatible = "qcom,smem";
255		memory-region = < 0x0e >;
256		hwlocks = < 0x0f 0x03 >;
257	};
258
259	smd {
260		compatible = "qcom,smd";
261
262		modem@0 {
263			interrupts = < 0x00 0x25 0x01 >;
264			qcom,ipc = < 0x10 0x08 0x03 >;
265			qcom,smd-edge = < 0x00 >;
266			status = "disabled";
267		};
268
269		q6@1 {
270			interrupts = < 0x00 0x5a 0x01 >;
271			qcom,ipc = < 0x10 0x08 0x0f >;
272			qcom,smd-edge = < 0x01 >;
273			status = "disabled";
274		};
275
276		dsps@3 {
277			interrupts = < 0x00 0x8a 0x01 >;
278			qcom,ipc = < 0x11 0x4080 0x00 >;
279			qcom,smd-edge = < 0x03 >;
280			status = "disabled";
281		};
282
283		riva@6 {
284			interrupts = < 0x00 0xc6 0x01 >;
285			qcom,ipc = < 0x10 0x08 0x19 >;
286			qcom,smd-edge = < 0x06 >;
287			status = "disabled";
288		};
289	};
290
291	smsm {
292		compatible = "qcom,smsm";
293		#address-cells = < 0x01 >;
294		#size-cells = < 0x00 >;
295		qcom,ipc-1 = < 0x10 0x08 0x04 >;
296		qcom,ipc-2 = < 0x10 0x08 0x0e >;
297		qcom,ipc-3 = < 0x10 0x08 0x17 >;
298		qcom,ipc-4 = < 0x11 0x4094 0x00 >;
299
300		apps@0 {
301			reg = < 0x00 >;
302			#qcom,smem-state-cells = < 0x01 >;
303			phandle = < 0x5b >;
304		};
305
306		modem@1 {
307			reg = < 0x01 >;
308			interrupts = < 0x00 0x26 0x01 >;
309			interrupt-controller;
310			#interrupt-cells = < 0x02 >;
311		};
312
313		q6@2 {
314			reg = < 0x02 >;
315			interrupts = < 0x00 0x59 0x01 >;
316			interrupt-controller;
317			#interrupt-cells = < 0x02 >;
318		};
319
320		wcnss@3 {
321			reg = < 0x03 >;
322			interrupts = < 0x00 0xcc 0x01 >;
323			interrupt-controller;
324			#interrupt-cells = < 0x02 >;
325			phandle = < 0x54 >;
326		};
327
328		dsps@4 {
329			reg = < 0x04 >;
330			interrupts = < 0x00 0x89 0x01 >;
331			interrupt-controller;
332			#interrupt-cells = < 0x02 >;
333		};
334	};
335
336	firmware {
337
338		scm {
339			compatible = "qcom,scm-apq8064";
340			clocks = < 0x12 0x0a >;
341			clock-names = "core";
342		};
343	};
344
345	iio-hwmon {
346		compatible = "iio-hwmon";
347		io-channels = < 0x13 0x00 0x01 0x13 0x00 0x02 0x13 0x00 0x04 0x13 0x00 0x0b 0x13 0x00 0x0c 0x13 0x00 0x0d 0x13 0x00 0x0e >;
348	};
349
350	soc {
351		#address-cells = < 0x01 >;
352		#size-cells = < 0x01 >;
353		ranges;
354		compatible = "simple-bus";
355
356		pinctrl@800000 {
357			compatible = "qcom,apq8064-pinctrl";
358			reg = < 0x800000 0x4000 >;
359			gpio-controller;
360			#gpio-cells = < 0x02 >;
361			interrupt-controller;
362			#interrupt-cells = < 0x02 >;
363			interrupts = < 0x00 0x10 0x04 >;
364			pinctrl-names = "default";
365			pinctrl-0 = < 0x14 >;
366			phandle = < 0x20 >;
367
368			sdc4-gpios {
369				phandle = < 0x40 >;
370
371				pios {
372					pins = "gpio63\0gpio64\0gpio65\0gpio66\0gpio67\0gpio68";
373					function = "sdc4";
374				};
375			};
376
377			sdcc1-pin-active {
378				phandle = < 0x39 >;
379
380				clk {
381					pins = "sdc1_clk";
382					drive-strengh = < 0x10 >;
383					bias-disable;
384				};
385
386				cmd {
387					pins = "sdc1_cmd";
388					drive-strengh = < 0x0a >;
389					bias-pull-up;
390				};
391
392				data {
393					pins = "sdc1_data";
394					drive-strengh = < 0x0a >;
395					bias-pull-up;
396				};
397			};
398
399			sdcc3-pin-active {
400
401				clk {
402					pins = "sdc3_clk";
403					drive-strengh = < 0x08 >;
404					bias-disable;
405				};
406
407				cmd {
408					pins = "sdc3_cmd";
409					drive-strengh = < 0x08 >;
410					bias-pull-up;
411				};
412
413				data {
414					pins = "sdc3_data";
415					drive-strengh = < 0x08 >;
416					bias-pull-up;
417				};
418			};
419
420			ps_hold {
421				phandle = < 0x14 >;
422
423				mux {
424					pins = "gpio78";
425					function = "ps_hold";
426				};
427			};
428
429			i2c1 {
430				phandle = < 0x16 >;
431
432				mux {
433					pins = "gpio20\0gpio21";
434					function = "gsbi1";
435				};
436
437				pinconf {
438					pins = "gpio20\0gpio21";
439					drive-strength = < 0x10 >;
440					bias-disable;
441				};
442			};
443
444			i2c1_pins_sleep {
445				phandle = < 0x17 >;
446
447				mux {
448					pins = "gpio20\0gpio21";
449					function = "gpio";
450				};
451
452				pinconf {
453					pins = "gpio20\0gpio21";
454					drive-strength = < 0x02 >;
455					bias-disable = < 0x00 >;
456				};
457			};
458
459			gsbi1_uart_2pins {
460
461				mux {
462					pins = "gpio18\0gpio19";
463					function = "gsbi1";
464				};
465			};
466
467			gsbi1_uart_4pins {
468
469				mux {
470					pins = "gpio18\0gpio19\0gpio20\0gpio21";
471					function = "gsbi1";
472				};
473			};
474
475			i2c2 {
476				phandle = < 0x18 >;
477
478				mux {
479					pins = "gpio24\0gpio25";
480					function = "gsbi2";
481				};
482
483				pinconf {
484					pins = "gpio24\0gpio25";
485					drive-strength = < 0x10 >;
486					bias-disable;
487				};
488			};
489
490			i2c2_pins_sleep {
491				phandle = < 0x19 >;
492
493				mux {
494					pins = "gpio24\0gpio25";
495					function = "gpio";
496				};
497
498				pinconf {
499					pins = "gpio24\0gpio25";
500					drive-strength = < 0x02 >;
501					bias-disable = < 0x00 >;
502				};
503			};
504
505			i2c3 {
506				phandle = < 0x1a >;
507
508				mux {
509					pins = "gpio8\0gpio9";
510					function = "gsbi3";
511				};
512
513				pinconf {
514					pins = "gpio8\0gpio9";
515					drive-strength = < 0x10 >;
516					bias-disable;
517				};
518			};
519
520			i2c3_pins_sleep {
521				phandle = < 0x1b >;
522
523				mux {
524					pins = "gpio8\0gpio9";
525					function = "gpio";
526				};
527
528				pinconf {
529					pins = "gpio8\0gpio9";
530					drive-strength = < 0x02 >;
531					bias-disable = < 0x00 >;
532				};
533			};
534
535			i2c4 {
536				phandle = < 0x1c >;
537
538				mux {
539					pins = "gpio12\0gpio13";
540					function = "gsbi4";
541				};
542
543				pinconf {
544					pins = "gpio12\0gpio13";
545					drive-strength = < 0x10 >;
546					bias-disable;
547				};
548			};
549
550			i2c4_pins_sleep {
551				phandle = < 0x1d >;
552
553				mux {
554					pins = "gpio12\0gpio13";
555					function = "gpio";
556				};
557
558				pinconf {
559					pins = "gpio12\0gpio13";
560					drive-strength = < 0x02 >;
561					bias-disable = < 0x00 >;
562				};
563			};
564
565			spi5_default {
566				phandle = < 0x1e >;
567
568				pinmux {
569					pins = "gpio51\0gpio52\0gpio54";
570					function = "gsbi5";
571				};
572
573				pinmux_cs {
574					function = "gpio";
575					pins = "gpio53";
576				};
577
578				pinconf {
579					pins = "gpio51\0gpio52\0gpio54";
580					drive-strength = < 0x10 >;
581					bias-disable;
582				};
583
584				pinconf_cs {
585					pins = "gpio53";
586					drive-strength = < 0x10 >;
587					bias-disable;
588					output-high;
589				};
590			};
591
592			spi5_sleep {
593				phandle = < 0x1f >;
594
595				pinmux {
596					function = "gpio";
597					pins = "gpio51\0gpio52\0gpio53\0gpio54";
598				};
599
600				pinconf {
601					pins = "gpio51\0gpio52\0gpio53\0gpio54";
602					drive-strength = < 0x02 >;
603					bias-pull-down;
604				};
605			};
606
607			i2c6 {
608				phandle = < 0x22 >;
609
610				mux {
611					pins = "gpio16\0gpio17";
612					function = "gsbi6";
613				};
614
615				pinconf {
616					pins = "gpio16\0gpio17";
617					drive-strength = < 0x10 >;
618					bias-disable;
619				};
620			};
621
622			i2c6_pins_sleep {
623				phandle = < 0x23 >;
624
625				mux {
626					pins = "gpio16\0gpio17";
627					function = "gpio";
628				};
629
630				pinconf {
631					pins = "gpio16\0gpio17";
632					drive-strength = < 0x02 >;
633					bias-disable = < 0x00 >;
634				};
635			};
636
637			gsbi6_uart_2pins {
638
639				mux {
640					pins = "gpio14\0gpio15";
641					function = "gsbi6";
642				};
643			};
644
645			gsbi6_uart_4pins {
646				phandle = < 0x21 >;
647
648				mux {
649					pins = "gpio14\0gpio15\0gpio16\0gpio17";
650					function = "gsbi6";
651				};
652			};
653
654			gsbi7_uart_2pins {
655				phandle = < 0x24 >;
656
657				mux {
658					pins = "gpio82\0gpio83";
659					function = "gsbi7";
660				};
661			};
662
663			gsbi7_uart_4pins {
664
665				mux {
666					pins = "gpio82\0gpio83\0gpio84\0gpio85";
667					function = "gsbi7";
668				};
669			};
670
671			i2c7 {
672				phandle = < 0x25 >;
673
674				mux {
675					pins = "gpio84\0gpio85";
676					function = "gsbi7";
677				};
678
679				pinconf {
680					pins = "gpio84\0gpio85";
681					drive-strength = < 0x10 >;
682					bias-disable;
683				};
684			};
685
686			i2c7_pins_sleep {
687				phandle = < 0x26 >;
688
689				mux {
690					pins = "gpio84\0gpio85";
691					function = "gpio";
692				};
693
694				pinconf {
695					pins = "gpio84\0gpio85";
696					drive-strength = < 0x02 >;
697					bias-disable = < 0x00 >;
698				};
699			};
700
701			riva-fm-active {
702				pins = "gpio14\0gpio15";
703				function = "riva_fm";
704			};
705
706			riva-bt-active {
707				pins = "gpio16\0gpio17";
708				function = "riva_bt";
709			};
710
711			riva-wlan-active {
712				pins = "gpio64\0gpio65\0gpio66\0gpio67\0gpio68";
713				function = "riva_wlan";
714				drive-strength = < 0x06 >;
715				bias-pull-down;
716			};
717
718			hdmi-pinctrl {
719				phandle = < 0x4c >;
720
721				mux {
722					pins = "gpio70\0gpio71\0gpio72";
723					function = "hdmi";
724				};
725
726				pinconf_ddc {
727					pins = "gpio70\0gpio71";
728					bias-pull-up;
729					drive-strength = < 0x02 >;
730				};
731
732				pinconf_hpd {
733					pins = "gpio72";
734					bias-pull-down;
735					drive-strength = < 0x10 >;
736				};
737			};
738
739			card_detect {
740				phandle = < 0x3e >;
741
742				mux {
743					pins = "gpio26";
744					function = "gpio";
745					bias-disable;
746				};
747			};
748
749			pcie_pinmux {
750				phandle = < 0x4b >;
751
752				mux {
753					pins = "gpio27";
754					function = "gpio";
755				};
756
757				conf {
758					pins = "gpio27";
759					drive-strength = < 0x0c >;
760					bias-disable;
761				};
762			};
763		};
764
765		syscon@1200000 {
766			compatible = "syscon";
767			reg = < 0x1200000 0x8000 >;
768			phandle = < 0x0d >;
769		};
770
771		interrupt-controller@2000000 {
772			compatible = "qcom,msm-qgic2";
773			interrupt-controller;
774			#interrupt-cells = < 0x03 >;
775			reg = < 0x2000000 0x1000 0x2002000 0x1000 >;
776			phandle = < 0x01 >;
777		};
778
779		timer@200a000 {
780			compatible = "qcom,kpss-timer\0qcom,kpss-wdt-apq8064\0qcom,msm-timer";
781			interrupts = < 0x01 0x01 0x301 0x01 0x02 0x301 0x01 0x03 0x301 >;
782			reg = < 0x200a000 0x100 >;
783			clock-frequency = < 0x19bfcc0 0x8000 >;
784			cpu-offset = < 0x80000 >;
785		};
786
787		clock-controller@2088000 {
788			compatible = "qcom,kpss-acc-v1";
789			reg = < 0x2088000 0x1000 0x2008000 0x1000 >;
790			phandle = < 0x03 >;
791		};
792
793		clock-controller@2098000 {
794			compatible = "qcom,kpss-acc-v1";
795			reg = < 0x2098000 0x1000 0x2008000 0x1000 >;
796			phandle = < 0x06 >;
797		};
798
799		clock-controller@20a8000 {
800			compatible = "qcom,kpss-acc-v1";
801			reg = < 0x20a8000 0x1000 0x2008000 0x1000 >;
802			phandle = < 0x08 >;
803		};
804
805		clock-controller@20b8000 {
806			compatible = "qcom,kpss-acc-v1";
807			reg = < 0x20b8000 0x1000 0x2008000 0x1000 >;
808			phandle = < 0x0a >;
809		};
810
811		power-controller@2089000 {
812			compatible = "qcom,apq8064-saw2-v1.1-cpu\0qcom,saw2";
813			reg = < 0x2089000 0x1000 0x2009000 0x1000 >;
814			regulator;
815			phandle = < 0x04 >;
816		};
817
818		power-controller@2099000 {
819			compatible = "qcom,apq8064-saw2-v1.1-cpu\0qcom,saw2";
820			reg = < 0x2099000 0x1000 0x2009000 0x1000 >;
821			regulator;
822			phandle = < 0x07 >;
823		};
824
825		power-controller@20a9000 {
826			compatible = "qcom,apq8064-saw2-v1.1-cpu\0qcom,saw2";
827			reg = < 0x20a9000 0x1000 0x2009000 0x1000 >;
828			regulator;
829			phandle = < 0x09 >;
830		};
831
832		power-controller@20b9000 {
833			compatible = "qcom,apq8064-saw2-v1.1-cpu\0qcom,saw2";
834			reg = < 0x20b9000 0x1000 0x2009000 0x1000 >;
835			regulator;
836			phandle = < 0x0b >;
837		};
838
839		sps-sic-non-secure@12100000 {
840			compatible = "syscon";
841			reg = < 0x12100000 0x10000 >;
842			phandle = < 0x11 >;
843		};
844
845		gsbi@12440000 {
846			status = "okay";
847			compatible = "qcom,gsbi-v1.0.0";
848			cell-index = < 0x01 >;
849			reg = < 0x12440000 0x100 >;
850			clocks = < 0x0c 0x93 >;
851			clock-names = "iface";
852			#address-cells = < 0x01 >;
853			#size-cells = < 0x01 >;
854			ranges;
855			syscon-tcsr = < 0x15 >;
856			qcom,mode = < 0x02 >;
857
858			serial@12450000 {
859				compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
860				reg = < 0x12450000 0x100 0x12400000 0x03 >;
861				interrupts = < 0x00 0xc1 0x04 >;
862				clocks = < 0x0c 0xa0 0x0c 0x93 >;
863				clock-names = "core\0iface";
864				status = "disabled";
865			};
866
867			i2c@12460000 {
868				compatible = "qcom,i2c-qup-v1.1.1";
869				pinctrl-0 = < 0x16 >;
870				pinctrl-1 = < 0x17 >;
871				pinctrl-names = "default\0sleep";
872				reg = < 0x12460000 0x1000 >;
873				interrupts = < 0x00 0xc2 0x04 >;
874				clocks = < 0x0c 0xb8 0x0c 0x93 >;
875				clock-names = "core\0iface";
876				#address-cells = < 0x01 >;
877				#size-cells = < 0x00 >;
878				status = "okay";
879				clock-frequency = < 0x30d40 >;
880
881				eeprom@52 {
882					compatible = "atmel,24c128";
883					reg = < 0x52 >;
884					pagesize = < 0x20 >;
885				};
886			};
887		};
888
889		gsbi@12480000 {
890			status = "disabled";
891			compatible = "qcom,gsbi-v1.0.0";
892			cell-index = < 0x02 >;
893			reg = < 0x12480000 0x100 >;
894			clocks = < 0x0c 0x94 >;
895			clock-names = "iface";
896			#address-cells = < 0x01 >;
897			#size-cells = < 0x01 >;
898			ranges;
899			syscon-tcsr = < 0x15 >;
900
901			i2c@124a0000 {
902				compatible = "qcom,i2c-qup-v1.1.1";
903				reg = < 0x124a0000 0x1000 >;
904				pinctrl-0 = < 0x18 >;
905				pinctrl-1 = < 0x19 >;
906				pinctrl-names = "default\0sleep";
907				interrupts = < 0x00 0xc4 0x04 >;
908				clocks = < 0x0c 0xba 0x0c 0x94 >;
909				clock-names = "core\0iface";
910				#address-cells = < 0x01 >;
911				#size-cells = < 0x00 >;
912				status = "disabled";
913			};
914		};
915
916		gsbi@16200000 {
917			status = "okay";
918			compatible = "qcom,gsbi-v1.0.0";
919			cell-index = < 0x03 >;
920			reg = < 0x16200000 0x100 >;
921			clocks = < 0x0c 0x95 >;
922			clock-names = "iface";
923			#address-cells = < 0x01 >;
924			#size-cells = < 0x01 >;
925			ranges;
926			qcom,mode = < 0x02 >;
927
928			i2c@16280000 {
929				compatible = "qcom,i2c-qup-v1.1.1";
930				pinctrl-0 = < 0x1a >;
931				pinctrl-1 = < 0x1b >;
932				pinctrl-names = "default\0sleep";
933				reg = < 0x16280000 0x1000 >;
934				interrupts = < 0x00 0x97 0x04 >;
935				clocks = < 0x0c 0xbc 0x0c 0x95 >;
936				clock-names = "core\0iface";
937				#address-cells = < 0x01 >;
938				#size-cells = < 0x00 >;
939				status = "okay";
940			};
941		};
942
943		gsbi@16300000 {
944			status = "okay";
945			compatible = "qcom,gsbi-v1.0.0";
946			cell-index = < 0x04 >;
947			reg = < 0x16300000 0x03 >;
948			clocks = < 0x0c 0x96 >;
949			clock-names = "iface";
950			#address-cells = < 0x01 >;
951			#size-cells = < 0x01 >;
952			ranges;
953			qcom,mode = < 0x02 >;
954
955			i2c@16380000 {
956				compatible = "qcom,i2c-qup-v1.1.1";
957				pinctrl-0 = < 0x1c >;
958				pinctrl-1 = < 0x1d >;
959				pinctrl-names = "default\0sleep";
960				reg = < 0x16380000 0x1000 >;
961				interrupts = < 0x00 0x99 0x04 >;
962				clocks = < 0x0c 0xbe 0x0c 0x96 >;
963				clock-names = "core\0iface";
964				status = "okay";
965			};
966		};
967
968		gsbi@1a200000 {
969			status = "okay";
970			compatible = "qcom,gsbi-v1.0.0";
971			cell-index = < 0x05 >;
972			reg = < 0x1a200000 0x03 >;
973			clocks = < 0x0c 0x97 >;
974			clock-names = "iface";
975			#address-cells = < 0x01 >;
976			#size-cells = < 0x01 >;
977			ranges;
978			qcom,mode = < 0x03 >;
979
980			serial@1a240000 {
981				compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
982				reg = < 0x1a240000 0x100 0x1a200000 0x03 >;
983				interrupts = < 0x00 0x9a 0x04 >;
984				clocks = < 0x0c 0xa8 0x0c 0x97 >;
985				clock-names = "core\0iface";
986				status = "disabled";
987			};
988
989			spi@1a280000 {
990				compatible = "qcom,spi-qup-v1.1.1";
991				reg = < 0x1a280000 0x1000 >;
992				interrupts = < 0x00 0x9b 0x04 >;
993				pinctrl-0 = < 0x1e >;
994				pinctrl-1 = < 0x1f >;
995				pinctrl-names = "default\0sleep";
996				clocks = < 0x0c 0xc0 0x0c 0x97 >;
997				clock-names = "core\0iface";
998				status = "okay";
999				#address-cells = < 0x01 >;
1000				#size-cells = < 0x00 >;
1001				num-cs = < 0x01 >;
1002				cs-gpios = < 0x20 0x35 0x00 >;
1003			};
1004		};
1005
1006		gsbi@16500000 {
1007			status = "ok";
1008			compatible = "qcom,gsbi-v1.0.0";
1009			cell-index = < 0x06 >;
1010			reg = < 0x16500000 0x03 >;
1011			clocks = < 0x0c 0x98 >;
1012			clock-names = "iface";
1013			#address-cells = < 0x01 >;
1014			#size-cells = < 0x01 >;
1015			ranges;
1016			qcom,mode = < 0x04 >;
1017
1018			serial@16540000 {
1019				compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
1020				reg = < 0x16540000 0x100 0x16500000 0x03 >;
1021				interrupts = < 0x00 0x9c 0x04 >;
1022				clocks = < 0x0c 0xaa 0x0c 0x98 >;
1023				clock-names = "core\0iface";
1024				status = "ok";
1025				pinctrl-names = "default";
1026				pinctrl-0 = < 0x21 >;
1027			};
1028
1029			i2c@16580000 {
1030				compatible = "qcom,i2c-qup-v1.1.1";
1031				pinctrl-0 = < 0x22 >;
1032				pinctrl-1 = < 0x23 >;
1033				pinctrl-names = "default\0sleep";
1034				reg = < 0x16580000 0x1000 >;
1035				interrupts = < 0x00 0x9d 0x04 >;
1036				clocks = < 0x0c 0xc2 0x0c 0x98 >;
1037				clock-names = "core\0iface";
1038				status = "disabled";
1039			};
1040		};
1041
1042		gsbi@16600000 {
1043			status = "ok";
1044			compatible = "qcom,gsbi-v1.0.0";
1045			cell-index = < 0x07 >;
1046			reg = < 0x16600000 0x100 >;
1047			clocks = < 0x0c 0x99 >;
1048			clock-names = "iface";
1049			#address-cells = < 0x01 >;
1050			#size-cells = < 0x01 >;
1051			ranges;
1052			syscon-tcsr = < 0x15 >;
1053			qcom,mode = < 0x06 >;
1054
1055			serial@16640000 {
1056				compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
1057				reg = < 0x16640000 0x1000 0x16600000 0x1000 >;
1058				interrupts = < 0x00 0x9e 0x04 >;
1059				clocks = < 0x0c 0xac 0x0c 0x99 >;
1060				clock-names = "core\0iface";
1061				status = "ok";
1062				pinctrl-names = "default";
1063				pinctrl-0 = < 0x24 >;
1064			};
1065
1066			i2c@16680000 {
1067				compatible = "qcom,i2c-qup-v1.1.1";
1068				pinctrl-0 = < 0x25 >;
1069				pinctrl-1 = < 0x26 >;
1070				pinctrl-names = "default\0sleep";
1071				reg = < 0x16680000 0x1000 >;
1072				interrupts = < 0x00 0x9f 0x04 >;
1073				clocks = < 0x0c 0xc4 0x0c 0x99 >;
1074				clock-names = "core\0iface";
1075				status = "disabled";
1076			};
1077		};
1078
1079		rng@1a500000 {
1080			compatible = "qcom,prng";
1081			reg = < 0x1a500000 0x200 >;
1082			clocks = < 0x0c 0x108 >;
1083			clock-names = "core";
1084		};
1085
1086		ssbi@c00000 {
1087			compatible = "qcom,ssbi";
1088			reg = < 0xc00000 0x1000 >;
1089			qcom,controller-type = "pmic-arbiter";
1090
1091			pmic@1 {
1092				compatible = "qcom,pm8821";
1093				interrupt-parent = < 0x20 >;
1094				interrupts = < 0x4c 0x08 >;
1095				#interrupt-cells = < 0x02 >;
1096				interrupt-controller;
1097				#address-cells = < 0x01 >;
1098				#size-cells = < 0x00 >;
1099
1100				mpps@50 {
1101					compatible = "qcom,pm8821-mpp\0qcom,ssbi-mpp";
1102					reg = < 0x50 >;
1103					interrupts = < 0x18 0x00 0x19 0x00 0x1a 0x00 0x1b 0x00 >;
1104					gpio-controller;
1105					#gpio-cells = < 0x02 >;
1106				};
1107			};
1108		};
1109
1110		qcom,ssbi@500000 {
1111			compatible = "qcom,ssbi";
1112			reg = < 0x500000 0x1000 >;
1113			qcom,controller-type = "pmic-arbiter";
1114
1115			pmic@0 {
1116				compatible = "qcom,pm8921";
1117				interrupt-parent = < 0x20 >;
1118				interrupts = < 0x4a 0x08 >;
1119				#interrupt-cells = < 0x02 >;
1120				interrupt-controller;
1121				#address-cells = < 0x01 >;
1122				#size-cells = < 0x00 >;
1123				phandle = < 0x27 >;
1124
1125				gpio@150 {
1126					compatible = "qcom,pm8921-gpio\0qcom,ssbi-gpio";
1127					reg = < 0x150 >;
1128					interrupts = < 0xc0 0x00 0xc1 0x00 0xc2 0x00 0xc3 0x00 0xc4 0x00 0xc5 0x00 0xc6 0x00 0xc7 0x00 0xc8 0x00 0xc9 0x00 0xca 0x00 0xcb 0x00 0xcc 0x00 0xcd 0x00 0xce 0x00 0xcf 0x00 0xd0 0x00 0xd1 0x00 0xd2 0x00 0xd3 0x00 0xd4 0x00 0xd5 0x00 0xd6 0x00 0xd7 0x00 0xd8 0x00 0xd9 0x00 0xda 0x00 0xdb 0x00 0xdc 0x00 0xdd 0x00 0xde 0x00 0xdf 0x00 0xe0 0x00 0xe1 0x00 0xe2 0x00 0xe3 0x00 0xe4 0x00 0xe5 0x00 0xe6 0x00 0xe7 0x00 0xe8 0x00 0xe9 0x00 0xea 0x00 0xeb 0x00 >;
1129					gpio-controller;
1130					#gpio-cells = < 0x02 >;
1131					phandle = < 0x6f >;
1132
1133					wlan-gpios {
1134						phandle = < 0x6e >;
1135
1136						pios {
1137							pins = "gpio43";
1138							function = "normal";
1139							bias-disable;
1140							power-source = < 0x02 >;
1141						};
1142					};
1143
1144					nled {
1145						phandle = < 0x70 >;
1146
1147						pios {
1148							pins = "gpio18";
1149							function = "normal";
1150							bias-disable;
1151							power-source = < 0x02 >;
1152						};
1153					};
1154				};
1155
1156				mpps@50 {
1157					compatible = "qcom,pm8921-mpp\0qcom,ssbi-mpp";
1158					reg = < 0x50 >;
1159					gpio-controller;
1160					#gpio-cells = < 0x02 >;
1161					interrupts = < 0x80 0x00 0x81 0x00 0x82 0x00 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x00 0x87 0x00 0x88 0x00 0x89 0x00 0x8a 0x00 0x8b 0x00 >;
1162				};
1163
1164				rtc@11d {
1165					compatible = "qcom,pm8921-rtc";
1166					interrupt-parent = < 0x27 >;
1167					interrupts = < 0x27 0x01 >;
1168					reg = < 0x11d >;
1169					allow-set-time;
1170				};
1171
1172				pwrkey@1c {
1173					compatible = "qcom,pm8921-pwrkey";
1174					reg = < 0x1c >;
1175					interrupt-parent = < 0x27 >;
1176					interrupts = < 0x32 0x01 0x33 0x01 >;
1177					debounce = < 0x3d09 >;
1178					pull-up;
1179				};
1180
1181				xoadc@197 {
1182					compatible = "qcom,pm8921-adc";
1183					reg = < 0xc5 >;
1184					interrupts-extended = < 0x27 0x4e 0x01 >;
1185					#address-cells = < 0x02 >;
1186					#size-cells = < 0x00 >;
1187					#io-channel-cells = < 0x02 >;
1188					phandle = < 0x13 >;
1189
1190					adc-channel@00 {
1191						reg = < 0x00 0x00 >;
1192					};
1193
1194					adc-channel@01 {
1195						reg = < 0x00 0x01 >;
1196					};
1197
1198					adc-channel@02 {
1199						reg = < 0x00 0x02 >;
1200					};
1201
1202					adc-channel@04 {
1203						reg = < 0x00 0x04 >;
1204					};
1205
1206					adc-channel@08 {
1207						reg = < 0x00 0x08 >;
1208					};
1209
1210					adc-channel@09 {
1211						reg = < 0x00 0x09 >;
1212					};
1213
1214					adc-channel@0a {
1215						reg = < 0x00 0x0a >;
1216					};
1217
1218					adc-channel@0b {
1219						reg = < 0x00 0x0b >;
1220					};
1221
1222					adc-channel@0c {
1223						reg = < 0x00 0x0c >;
1224					};
1225
1226					adc-channel@0d {
1227						reg = < 0x00 0x0d >;
1228					};
1229
1230					adc-channel@0e {
1231						reg = < 0x00 0x0e >;
1232					};
1233
1234					adc-channel@0f {
1235						reg = < 0x00 0x0f >;
1236					};
1237				};
1238			};
1239		};
1240
1241		qfprom@700000 {
1242			compatible = "qcom,qfprom";
1243			reg = < 0x700000 0x1000 >;
1244			#address-cells = < 0x01 >;
1245			#size-cells = < 0x01 >;
1246			ranges;
1247
1248			calib {
1249				reg = < 0x404 0x10 >;
1250				phandle = < 0x28 >;
1251			};
1252
1253			backup_calib {
1254				reg = < 0x414 0x10 >;
1255				phandle = < 0x29 >;
1256			};
1257		};
1258
1259		clock-controller@900000 {
1260			compatible = "qcom,gcc-apq8064";
1261			reg = < 0x900000 0x4000 >;
1262			nvmem-cells = < 0x28 0x29 >;
1263			nvmem-cell-names = "calib\0calib_backup";
1264			#clock-cells = < 0x01 >;
1265			#reset-cells = < 0x01 >;
1266			#thermal-sensor-cells = < 0x01 >;
1267			phandle = < 0x0c >;
1268		};
1269
1270		clock-controller@28000000 {
1271			compatible = "qcom,lcc-apq8064";
1272			reg = < 0x28000000 0x1000 >;
1273			#clock-cells = < 0x01 >;
1274			#reset-cells = < 0x01 >;
1275		};
1276
1277		clock-controller@4000000 {
1278			compatible = "qcom,mmcc-apq8064";
1279			reg = < 0x4000000 0x1000 >;
1280			#clock-cells = < 0x01 >;
1281			#reset-cells = < 0x01 >;
1282			phandle = < 0x44 >;
1283		};
1284
1285		clock-controller@2011000 {
1286			compatible = "syscon";
1287			reg = < 0x2011000 0x1000 >;
1288			phandle = < 0x10 >;
1289		};
1290
1291		rpm@108000 {
1292			compatible = "qcom,rpm-apq8064";
1293			reg = < 0x108000 0x1000 >;
1294			qcom,ipc = < 0x10 0x08 0x02 >;
1295			interrupts = < 0x00 0x13 0x01 0x00 0x15 0x01 0x00 0x16 0x01 >;
1296			interrupt-names = "ack\0err\0wakeup";
1297
1298			clock-controller {
1299				compatible = "qcom,rpmcc-apq8064\0qcom,rpmcc";
1300				#clock-cells = < 0x01 >;
1301				phandle = < 0x12 >;
1302			};
1303
1304			regulators {
1305				compatible = "qcom,rpm-pm8921-regulators";
1306				vin_lvs1_3_6-supply = < 0x2a >;
1307				vin_lvs2-supply = < 0x2b >;
1308				vin_lvs4_5_7-supply = < 0x2a >;
1309				vdd_l1_l2_l12_l18-supply = < 0x2a >;
1310				vdd_l24-supply = < 0x2b >;
1311				vdd_l25-supply = < 0x2b >;
1312				vdd_l26-supply = < 0x2c >;
1313				vdd_l27-supply = < 0x2c >;
1314				vdd_l28-supply = < 0x2c >;
1315
1316				s1 {
1317					regulator-always-on;
1318					regulator-min-microvolt = < 0x12b128 >;
1319					regulator-max-microvolt = < 0x12b128 >;
1320					qcom,switch-mode-frequency = < 0x30d400 >;
1321					bias-pull-down;
1322					phandle = < 0x2b >;
1323				};
1324
1325				s2 {
1326					phandle = < 0x57 >;
1327				};
1328
1329				s3 {
1330					regulator-min-microvolt = < 0xf4240 >;
1331					regulator-max-microvolt = < 0x155cc0 >;
1332					qcom,switch-mode-frequency = < 0x493e00 >;
1333					phandle = < 0x49 >;
1334				};
1335
1336				s4 {
1337					regulator-min-microvolt = < 0x1b7740 >;
1338					regulator-max-microvolt = < 0x1b7740 >;
1339					qcom,switch-mode-frequency = < 0x30d400 >;
1340					phandle = < 0x2a >;
1341				};
1342
1343				s7 {
1344					regulator-min-microvolt = < 0x13d620 >;
1345					regulator-max-microvolt = < 0x13d620 >;
1346					qcom,switch-mode-frequency = < 0x30d400 >;
1347					phandle = < 0x2c >;
1348				};
1349
1350				s8 {
1351				};
1352
1353				l1 {
1354				};
1355
1356				l2 {
1357				};
1358
1359				l3 {
1360					regulator-min-microvolt = < 0x2e8a10 >;
1361					regulator-max-microvolt = < 0x325aa0 >;
1362					bias-pull-down;
1363					phandle = < 0x31 >;
1364				};
1365
1366				l4 {
1367					regulator-min-microvolt = < 0xf4240 >;
1368					regulator-max-microvolt = < 0x1b7740 >;
1369					bias-pull-down;
1370					phandle = < 0x32 >;
1371				};
1372
1373				l5 {
1374					regulator-min-microvolt = < 0x29f630 >;
1375					regulator-max-microvolt = < 0x2dc6c0 >;
1376					bias-pull-down;
1377					phandle = < 0x3b >;
1378				};
1379
1380				l6 {
1381					regulator-min-microvolt = < 0x2d0370 >;
1382					regulator-max-microvolt = < 0x2d0370 >;
1383					bias-pull-down;
1384					phandle = < 0x3d >;
1385				};
1386
1387				l7 {
1388				};
1389
1390				l8 {
1391				};
1392
1393				l9 {
1394				};
1395
1396				l10 {
1397					phandle = < 0x58 >;
1398				};
1399
1400				l11 {
1401				};
1402
1403				l12 {
1404				};
1405
1406				l14 {
1407				};
1408
1409				l15 {
1410				};
1411
1412				l16 {
1413				};
1414
1415				l17 {
1416				};
1417
1418				l18 {
1419				};
1420
1421				l21 {
1422				};
1423
1424				l22 {
1425				};
1426
1427				l23 {
1428					regulator-min-microvolt = < 0x19f0a0 >;
1429					regulator-max-microvolt = < 0x1cfde0 >;
1430					bias-pull-down;
1431					phandle = < 0x35 >;
1432				};
1433
1434				l24 {
1435					phandle = < 0x56 >;
1436				};
1437
1438				l25 {
1439				};
1440
1441				l26 {
1442				};
1443
1444				l27 {
1445				};
1446
1447				l28 {
1448				};
1449
1450				l29 {
1451				};
1452
1453				lvs1 {
1454					bias-pull-down;
1455					phandle = < 0x42 >;
1456				};
1457
1458				lvs2 {
1459					phandle = < 0x59 >;
1460				};
1461
1462				lvs3 {
1463				};
1464
1465				lvs4 {
1466				};
1467
1468				lvs5 {
1469				};
1470
1471				lvs6 {
1472					bias-pull-down;
1473					phandle = < 0x4a >;
1474				};
1475
1476				lvs7 {
1477				};
1478
1479				usb-switch {
1480				};
1481
1482				hdmi-switch {
1483					bias-pull-down;
1484					phandle = < 0x4e >;
1485				};
1486
1487				ncp {
1488				};
1489			};
1490		};
1491
1492		usb@12500000 {
1493			compatible = "qcom,ci-hdrc";
1494			reg = < 0x12500000 0x200 0x12500200 0x200 >;
1495			interrupts = < 0x00 0x64 0x04 >;
1496			clocks = < 0x0c 0x80 0x0c 0x7e >;
1497			clock-names = "core\0iface";
1498			assigned-clocks = < 0x0c 0x80 >;
1499			assigned-clock-rates = < 0x3938700 >;
1500			resets = < 0x0c 0x40 >;
1501			reset-names = "core";
1502			phy_type = "ulpi";
1503			ahb-burst-config = < 0x00 >;
1504			phys = < 0x2d >;
1505			phy-names = "usb-phy";
1506			status = "okay";
1507			#reset-cells = < 0x01 >;
1508			dr_mode = "otg";
1509			phandle = < 0x30 >;
1510
1511			ulpi {
1512
1513				phy {
1514					compatible = "qcom,usb-hs-phy-apq8064\0qcom,usb-hs-phy";
1515					clocks = < 0x2e 0x2f >;
1516					clock-names = "sleep\0ref";
1517					resets = < 0x30 0x00 >;
1518					reset-names = "por";
1519					#phy-cells = < 0x00 >;
1520					v3p3-supply = < 0x31 >;
1521					v1p8-supply = < 0x32 >;
1522					phandle = < 0x2d >;
1523				};
1524			};
1525		};
1526
1527		usb@12520000 {
1528			compatible = "qcom,ci-hdrc";
1529			reg = < 0x12520000 0x200 0x12520200 0x200 >;
1530			interrupts = < 0x00 0xbc 0x04 >;
1531			clocks = < 0x0c 0x129 0x0c 0x127 >;
1532			clock-names = "core\0iface";
1533			assigned-clocks = < 0x0c 0x129 >;
1534			assigned-clock-rates = < 0x3938700 >;
1535			resets = < 0x0c 0x64 >;
1536			reset-names = "core";
1537			phy_type = "ulpi";
1538			ahb-burst-config = < 0x00 >;
1539			phys = < 0x33 >;
1540			phy-names = "usb-phy";
1541			status = "okay";
1542			#reset-cells = < 0x01 >;
1543			dr_mode = "host";
1544			phandle = < 0x34 >;
1545
1546			ulpi {
1547
1548				phy {
1549					compatible = "qcom,usb-hs-phy-apq8064\0qcom,usb-hs-phy";
1550					#phy-cells = < 0x00 >;
1551					clocks = < 0x2e 0x2f >;
1552					clock-names = "sleep\0ref";
1553					resets = < 0x34 0x00 >;
1554					reset-names = "por";
1555					v3p3-supply = < 0x31 >;
1556					v1p8-supply = < 0x35 >;
1557					phandle = < 0x33 >;
1558				};
1559			};
1560		};
1561
1562		usb@12530000 {
1563			compatible = "qcom,ci-hdrc";
1564			reg = < 0x12530000 0x200 0x12530200 0x200 >;
1565			interrupts = < 0x00 0xd7 0x04 >;
1566			clocks = < 0x0c 0x12c 0x0c 0x12a >;
1567			clock-names = "core\0iface";
1568			assigned-clocks = < 0x0c 0x12c >;
1569			assigned-clock-rates = < 0x3938700 >;
1570			resets = < 0x0c 0x65 >;
1571			reset-names = "core";
1572			phy_type = "ulpi";
1573			ahb-burst-config = < 0x00 >;
1574			phys = < 0x36 >;
1575			phy-names = "usb-phy";
1576			status = "okay";
1577			#reset-cells = < 0x01 >;
1578			dr_mode = "host";
1579			phandle = < 0x37 >;
1580
1581			ulpi {
1582
1583				phy {
1584					compatible = "qcom,usb-hs-phy-apq8064\0qcom,usb-hs-phy";
1585					#phy-cells = < 0x00 >;
1586					clocks = < 0x2e 0x2f >;
1587					clock-names = "sleep\0ref";
1588					resets = < 0x37 0x00 >;
1589					reset-names = "por";
1590					v3p3-supply = < 0x31 >;
1591					v1p8-supply = < 0x35 >;
1592					phandle = < 0x36 >;
1593				};
1594			};
1595		};
1596
1597		phy@1b400000 {
1598			compatible = "qcom,apq8064-sata-phy";
1599			status = "okay";
1600			reg = < 0x1b400000 0x200 >;
1601			reg-names = "phy_mem";
1602			clocks = < 0x0c 0x12d >;
1603			clock-names = "cfg";
1604			#phy-cells = < 0x00 >;
1605			phandle = < 0x38 >;
1606		};
1607
1608		sata@29000000 {
1609			compatible = "qcom,apq8064-ahci\0generic-ahci";
1610			status = "okay";
1611			reg = < 0x29000000 0x180 >;
1612			interrupts = < 0x00 0xd1 0x04 >;
1613			clocks = < 0x0c 0x3b 0x0c 0xed 0x0c 0x12e 0x0c 0xef 0x0c 0xf0 >;
1614			clock-names = "slave_iface\0iface\0bus\0rxoob\0core_pmalive";
1615			assigned-clocks = < 0x0c 0xef 0x0c 0xf0 >;
1616			assigned-clock-rates = < 0x5f5e100 0x5f5e100 >;
1617			phys = < 0x38 >;
1618			phy-names = "sata-phy";
1619			ports-implemented = < 0x01 >;
1620			target-supply = < 0x2a >;
1621		};
1622
1623		dma@12402000 {
1624			compatible = "qcom,bam-v1.3.0";
1625			reg = < 0x12402000 0x8000 >;
1626			interrupts = < 0x00 0x62 0x04 >;
1627			clocks = < 0x0c 0x6e >;
1628			clock-names = "bam_clk";
1629			#dma-cells = < 0x01 >;
1630			qcom,ee = < 0x00 >;
1631			phandle = < 0x3a >;
1632		};
1633
1634		dma@12182000 {
1635			compatible = "qcom,bam-v1.3.0";
1636			reg = < 0x12182000 0x8000 >;
1637			interrupts = < 0x00 0x60 0x04 >;
1638			clocks = < 0x0c 0x70 >;
1639			clock-names = "bam_clk";
1640			#dma-cells = < 0x01 >;
1641			qcom,ee = < 0x00 >;
1642			phandle = < 0x3c >;
1643		};
1644
1645		dma@121c2000 {
1646			compatible = "qcom,bam-v1.3.0";
1647			reg = < 0x121c2000 0x8000 >;
1648			interrupts = < 0x00 0x5f 0x04 >;
1649			clocks = < 0x0c 0x71 >;
1650			clock-names = "bam_clk";
1651			#dma-cells = < 0x01 >;
1652			qcom,ee = < 0x00 >;
1653			phandle = < 0x3f >;
1654		};
1655
1656		amba {
1657			compatible = "simple-bus";
1658			#address-cells = < 0x01 >;
1659			#size-cells = < 0x01 >;
1660			ranges;
1661
1662			sdcc@12400000 {
1663				status = "okay";
1664				compatible = "arm,pl18x\0arm,primecell";
1665				pinctrl-names = "default";
1666				pinctrl-0 = < 0x39 >;
1667				arm,primecell-periphid = < 0x51180 >;
1668				reg = < 0x12400000 0x2000 >;
1669				interrupts = < 0x00 0x68 0x04 >;
1670				interrupt-names = "cmd_irq";
1671				clocks = < 0x0c 0x78 0x0c 0x6e >;
1672				clock-names = "mclk\0apb_pclk";
1673				bus-width = < 0x08 >;
1674				max-frequency = < 0x5b8d800 >;
1675				non-removable;
1676				cap-sd-highspeed;
1677				cap-mmc-highspeed;
1678				dmas = < 0x3a 0x02 0x3a 0x01 >;
1679				dma-names = "tx\0rx";
1680				vmmc-supply = < 0x3b >;
1681				vqmmc-supply = < 0x2a >;
1682			};
1683
1684			sdcc@12180000 {
1685				compatible = "arm,pl18x\0arm,primecell";
1686				arm,primecell-periphid = < 0x51180 >;
1687				status = "okay";
1688				reg = < 0x12180000 0x2000 >;
1689				interrupts = < 0x00 0x66 0x04 >;
1690				interrupt-names = "cmd_irq";
1691				clocks = < 0x0c 0x7a 0x0c 0x70 >;
1692				clock-names = "mclk\0apb_pclk";
1693				bus-width = < 0x04 >;
1694				cap-sd-highspeed;
1695				cap-mmc-highspeed;
1696				max-frequency = < 0xb71b000 >;
1697				no-1-8-v;
1698				dmas = < 0x3c 0x02 0x3c 0x01 >;
1699				dma-names = "tx\0rx";
1700				vmmc-supply = < 0x3d >;
1701				pinctrl-names = "default";
1702				pinctrl-0 = < 0x3e >;
1703				cd-gpios = < 0x20 0x1a 0x01 >;
1704			};
1705
1706			sdcc@121c0000 {
1707				compatible = "arm,pl18x\0arm,primecell";
1708				arm,primecell-periphid = < 0x51180 >;
1709				status = "okay";
1710				reg = < 0x121c0000 0x2000 >;
1711				interrupts = < 0x00 0x65 0x04 >;
1712				interrupt-names = "cmd_irq";
1713				clocks = < 0x0c 0x7b 0x0c 0x71 >;
1714				clock-names = "mclk\0apb_pclk";
1715				bus-width = < 0x04 >;
1716				cap-sd-highspeed;
1717				cap-mmc-highspeed;
1718				max-frequency = < 0x2dc6c00 >;
1719				dmas = < 0x3f 0x02 0x3f 0x01 >;
1720				dma-names = "tx\0rx";
1721				pinctrl-names = "default";
1722				pinctrl-0 = < 0x40 >;
1723				vmmc-supply = < 0x41 >;
1724				vqmmc-supply = < 0x42 >;
1725				mmc-pwrseq = < 0x43 >;
1726			};
1727		};
1728
1729		syscon@1a400000 {
1730			compatible = "qcom,tcsr-apq8064\0syscon";
1731			reg = < 0x1a400000 0x100 >;
1732			phandle = < 0x15 >;
1733		};
1734
1735		adreno-3xx@4300000 {
1736			compatible = "qcom,adreno-3xx";
1737			reg = < 0x4300000 0x20000 >;
1738			reg-names = "kgsl_3d0_reg_memory";
1739			interrupts = < 0x00 0x50 0x04 >;
1740			interrupt-names = "kgsl_3d0_irq";
1741			clock-names = "core_clk\0iface_clk\0mem_clk\0mem_iface_clk";
1742			clocks = < 0x44 0x47 0x44 0x16 0x44 0x21 0x44 0x13 >;
1743			qcom,chipid = < 0x3020002 >;
1744			iommus = < 0x45 0x00 0x45 0x01 0x45 0x02 0x45 0x03 0x45 0x04 0x45 0x05 0x45 0x06 0x45 0x07 0x45 0x08 0x45 0x09 0x45 0x0a 0x45 0x0b 0x45 0x0c 0x45 0x0d 0x45 0x0e 0x45 0x0f 0x45 0x10 0x45 0x11 0x45 0x12 0x45 0x13 0x45 0x14 0x45 0x15 0x45 0x16 0x45 0x17 0x45 0x18 0x45 0x19 0x45 0x1a 0x45 0x1b 0x45 0x1c 0x45 0x1d 0x45 0x1e 0x45 0x1f 0x46 0x00 0x46 0x01 0x46 0x02 0x46 0x03 0x46 0x04 0x46 0x05 0x46 0x06 0x46 0x07 0x46 0x08 0x46 0x09 0x46 0x0a 0x46 0x0b 0x46 0x0c 0x46 0x0d 0x46 0x0e 0x46 0x0f 0x46 0x10 0x46 0x11 0x46 0x12 0x46 0x13 0x46 0x14 0x46 0x15 0x46 0x16 0x46 0x17 0x46 0x18 0x46 0x19 0x46 0x1a 0x46 0x1b 0x46 0x1c 0x46 0x1d 0x46 0x1e 0x46 0x1f >;
1745
1746			qcom,gpu-pwrlevels {
1747				compatible = "qcom,gpu-pwrlevels";
1748
1749				qcom,gpu-pwrlevel@0 {
1750					qcom,gpu-freq = < 0x1ad27480 >;
1751				};
1752
1753				qcom,gpu-pwrlevel@1 {
1754					qcom,gpu-freq = < 0x19bfcc0 >;
1755				};
1756			};
1757		};
1758
1759		syscon@5700000 {
1760			compatible = "syscon";
1761			reg = < 0x5700000 0x70 >;
1762			phandle = < 0x48 >;
1763		};
1764
1765		mdss_dsi@4700000 {
1766			compatible = "qcom,mdss-dsi-ctrl";
1767			label = "MDSS DSI CTRL->0";
1768			#address-cells = < 0x01 >;
1769			#size-cells = < 0x00 >;
1770			interrupts = < 0x00 0x52 0x04 >;
1771			reg = < 0x4700000 0x200 >;
1772			reg-names = "dsi_ctrl";
1773			clocks = < 0x44 0x11 0x44 0x08 0x44 0x04 0x44 0x39 0x44 0x54 0x44 0x6a 0x44 0x58 >;
1774			clock-names = "iface_clk\0bus_clk\0core_mmss_clk\0src_clk\0byte_clk\0pixel_clk\0core_clk";
1775			assigned-clocks = < 0x44 0x53 0x44 0x57 0x44 0x38 0x44 0x69 >;
1776			assigned-clock-parents = < 0x47 0x00 0x47 0x00 0x47 0x01 0x47 0x01 >;
1777			syscon-sfpb = < 0x48 >;
1778			phys = < 0x47 >;
1779
1780			ports {
1781				#address-cells = < 0x01 >;
1782				#size-cells = < 0x00 >;
1783
1784				port@0 {
1785					reg = < 0x00 >;
1786
1787					endpoint {
1788					};
1789				};
1790
1791				port@1 {
1792					reg = < 0x01 >;
1793
1794					endpoint {
1795					};
1796				};
1797			};
1798		};
1799
1800		dsi-phy@4700200 {
1801			compatible = "qcom,dsi-phy-28nm-8960";
1802			#clock-cells = < 0x01 >;
1803			#phy-cells = < 0x00 >;
1804			reg = < 0x4700200 0x100 0x4700300 0x200 0x4700500 0x5c >;
1805			reg-names = "dsi_pll\0dsi_phy\0dsi_phy_regulator";
1806			clock-names = "iface_clk";
1807			clocks = < 0x44 0x11 >;
1808			phandle = < 0x47 >;
1809		};
1810
1811		iommu@7500000 {
1812			compatible = "qcom,apq8064-iommu";
1813			#iommu-cells = < 0x01 >;
1814			clock-names = "smmu_pclk\0iommu_clk";
1815			clocks = < 0x44 0x0b 0x44 0x1e >;
1816			reg = < 0x7500000 0x100000 >;
1817			interrupts = < 0x00 0x3f 0x04 0x00 0x40 0x04 >;
1818			qcom,ncb = < 0x02 >;
1819			phandle = < 0x51 >;
1820		};
1821
1822		iommu@7600000 {
1823			compatible = "qcom,apq8064-iommu";
1824			#iommu-cells = < 0x01 >;
1825			clock-names = "smmu_pclk\0iommu_clk";
1826			clocks = < 0x44 0x0b 0x44 0x1e >;
1827			reg = < 0x7600000 0x100000 >;
1828			interrupts = < 0x00 0x3d 0x04 0x00 0x3e 0x04 >;
1829			qcom,ncb = < 0x02 >;
1830			phandle = < 0x52 >;
1831		};
1832
1833		iommu@7c00000 {
1834			compatible = "qcom,apq8064-iommu";
1835			#iommu-cells = < 0x01 >;
1836			clock-names = "smmu_pclk\0iommu_clk";
1837			clocks = < 0x44 0x0b 0x44 0x21 >;
1838			reg = < 0x7c00000 0x100000 >;
1839			interrupts = < 0x00 0x45 0x04 0x00 0x46 0x04 >;
1840			qcom,ncb = < 0x03 >;
1841			phandle = < 0x45 >;
1842		};
1843
1844		iommu@7d00000 {
1845			compatible = "qcom,apq8064-iommu";
1846			#iommu-cells = < 0x01 >;
1847			clock-names = "smmu_pclk\0iommu_clk";
1848			clocks = < 0x44 0x0b 0x44 0x21 >;
1849			reg = < 0x7d00000 0x100000 >;
1850			interrupts = < 0x00 0xd2 0x04 0x00 0xd3 0x04 >;
1851			qcom,ncb = < 0x03 >;
1852			phandle = < 0x46 >;
1853		};
1854
1855		pci@1b500000 {
1856			compatible = "qcom,pcie-apq8064\0snps,dw-pcie";
1857			reg = < 0x1b500000 0x1000 0x1b502000 0x80 0x1b600000 0x100 0xff00000 0x100000 >;
1858			reg-names = "dbi\0elbi\0parf\0config";
1859			device_type = "pci";
1860			linux,pci-domain = < 0x00 >;
1861			bus-range = < 0x00 0xff >;
1862			num-lanes = < 0x01 >;
1863			#address-cells = < 0x03 >;
1864			#size-cells = < 0x02 >;
1865			ranges = < 0x81000000 0x00 0x00 0xfe00000 0x00 0x100000 0x82000000 0x00 0x8000000 0x8000000 0x00 0x7e00000 >;
1866			interrupts = < 0x00 0xee 0x04 >;
1867			interrupt-names = "msi";
1868			#interrupt-cells = < 0x01 >;
1869			interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
1870			interrupt-map = < 0x00 0x00 0x00 0x01 0x01 0x00 0x24 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x25 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x26 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x27 0x04 >;
1871			clocks = < 0x0c 0x2b 0x0c 0x2e 0x0c 0x2d >;
1872			clock-names = "core\0iface\0phy";
1873			resets = < 0x0c 0x6c 0x0c 0x6b 0x0c 0x6a 0x0c 0x69 0x0c 0x68 >;
1874			reset-names = "axi\0ahb\0por\0pci\0phy";
1875			status = "ok";
1876			vdda-supply = < 0x49 >;
1877			vdda_phy-supply = < 0x4a >;
1878			vdda_refclk-supply = < 0x41 >;
1879			pinctrl-0 = < 0x4b >;
1880			pinctrl-names = "default";
1881			perst-gpio = < 0x20 0x1b 0x01 >;
1882		};
1883
1884		hdmi-tx@4a00000 {
1885			compatible = "qcom,hdmi-tx-8960";
1886			pinctrl-names = "default";
1887			pinctrl-0 = < 0x4c >;
1888			reg = < 0x4a00000 0x2f0 >;
1889			reg-names = "core_physical";
1890			interrupts = < 0x00 0x4f 0x04 >;
1891			clocks = < 0x44 0x3e 0x44 0x0c 0x44 0x15 >;
1892			clock-names = "core_clk\0master_iface_clk\0slave_iface_clk";
1893			phys = < 0x4d >;
1894			phy-names = "hdmi-phy";
1895			status = "okay";
1896			core-vdda-supply = < 0x4e >;
1897			hdmi-mux-supply = < 0x41 >;
1898			hpd-gpios = < 0x20 0x48 0x00 >;
1899
1900			ports {
1901				#address-cells = < 0x01 >;
1902				#size-cells = < 0x00 >;
1903
1904				port@0 {
1905					reg = < 0x00 >;
1906
1907					endpoint {
1908						remote-endpoint = < 0x4f >;
1909						phandle = < 0x53 >;
1910					};
1911				};
1912
1913				port@1 {
1914					reg = < 0x01 >;
1915
1916					endpoint {
1917						remote-endpoint = < 0x50 >;
1918						phandle = < 0x71 >;
1919					};
1920				};
1921			};
1922		};
1923
1924		hdmi-phy@4a00400 {
1925			compatible = "qcom,hdmi-phy-8960";
1926			reg = < 0x4a00400 0x60 0x4a00500 0x100 >;
1927			reg-names = "hdmi_phy\0hdmi_pll";
1928			clocks = < 0x44 0x15 >;
1929			clock-names = "slave_iface_clk";
1930			#phy-cells = < 0x00 >;
1931			status = "okay";
1932			core-vdda-supply = < 0x4e >;
1933			phandle = < 0x4d >;
1934		};
1935
1936		mdp@5100000 {
1937			compatible = "qcom,mdp4";
1938			reg = < 0x5100000 0xf0000 >;
1939			interrupts = < 0x00 0x4b 0x04 >;
1940			clocks = < 0x44 0x4d 0x44 0x10 0x44 0x1e 0x44 0x4e 0x44 0x5f 0x44 0x60 >;
1941			clock-names = "core_clk\0iface_clk\0bus_clk\0lut_clk\0hdmi_clk\0tv_clk";
1942			iommus = < 0x51 0x00 0x51 0x02 0x52 0x00 0x52 0x02 >;
1943			status = "okay";
1944
1945			ports {
1946				#address-cells = < 0x01 >;
1947				#size-cells = < 0x00 >;
1948
1949				port@0 {
1950					reg = < 0x00 >;
1951
1952					endpoint {
1953					};
1954				};
1955
1956				port@1 {
1957					reg = < 0x01 >;
1958
1959					endpoint {
1960					};
1961				};
1962
1963				port@2 {
1964					reg = < 0x02 >;
1965
1966					endpoint {
1967					};
1968				};
1969
1970				port@3 {
1971					reg = < 0x03 >;
1972
1973					endpoint {
1974						remote-endpoint = < 0x53 >;
1975						phandle = < 0x4f >;
1976					};
1977				};
1978			};
1979		};
1980
1981		riva-pil@3204000 {
1982			compatible = "qcom,riva-pil";
1983			reg = < 0x3200800 0x1000 0x3202000 0x2000 0x3204000 0x100 >;
1984			reg-names = "ccu\0dxe\0pmu";
1985			interrupts-extended = < 0x01 0x00 0xc7 0x01 0x54 0x06 0x01 >;
1986			interrupt-names = "wdog\0fatal";
1987			memory-region = < 0x55 >;
1988			vddcx-supply = < 0x49 >;
1989			vddmx-supply = < 0x56 >;
1990			vddpx-supply = < 0x2a >;
1991			status = "disabled";
1992			phandle = < 0x5a >;
1993
1994			iris {
1995				compatible = "qcom,wcn3660";
1996				clocks = < 0x2f >;
1997				clock-names = "xo";
1998				vddxo-supply = < 0x32 >;
1999				vddrfa-supply = < 0x57 >;
2000				vddpa-supply = < 0x58 >;
2001				vdddig-supply = < 0x59 >;
2002			};
2003
2004			smd-edge {
2005				interrupts = < 0x00 0xc6 0x01 >;
2006				qcom,ipc = < 0x10 0x08 0x19 >;
2007				qcom,smd-edge = < 0x06 >;
2008				label = "riva";
2009
2010				wcnss {
2011					compatible = "qcom,wcnss";
2012					qcom,smd-channels = "WCNSS_CTRL";
2013					qcom,mmio = < 0x5a >;
2014
2015					bt {
2016						compatible = "qcom,wcnss-bt";
2017					};
2018
2019					wifi {
2020						compatible = "qcom,wcnss-wlan";
2021						interrupts = < 0x00 0xcb 0x04 0x00 0xca 0x04 >;
2022						interrupt-names = "tx\0rx";
2023						qcom,smem-states = < 0x5b 0x0a 0x5b 0x09 >;
2024						qcom,smem-state-names = "tx-enable\0tx-rings-empty";
2025					};
2026				};
2027			};
2028		};
2029
2030		etb@1a01000 {
2031			compatible = "coresight-etb10\0arm,primecell";
2032			reg = < 0x1a01000 0x1000 >;
2033			clocks = < 0x12 0x08 >;
2034			clock-names = "apb_pclk";
2035
2036			in-ports {
2037
2038				port {
2039
2040					endpoint {
2041						remote-endpoint = < 0x5c >;
2042						phandle = < 0x5e >;
2043					};
2044				};
2045			};
2046		};
2047
2048		tpiu@1a03000 {
2049			compatible = "arm,coresight-tpiu\0arm,primecell";
2050			reg = < 0x1a03000 0x1000 >;
2051			clocks = < 0x12 0x08 >;
2052			clock-names = "apb_pclk";
2053
2054			in-ports {
2055
2056				port {
2057
2058					endpoint {
2059						remote-endpoint = < 0x5d >;
2060						phandle = < 0x5f >;
2061					};
2062				};
2063			};
2064		};
2065
2066		replicator {
2067			compatible = "arm,coresight-replicator";
2068			clocks = < 0x12 0x08 >;
2069			clock-names = "apb_pclk";
2070
2071			out-ports {
2072				#address-cells = < 0x01 >;
2073				#size-cells = < 0x00 >;
2074
2075				port@0 {
2076					reg = < 0x00 >;
2077
2078					endpoint {
2079						remote-endpoint = < 0x5e >;
2080						phandle = < 0x5c >;
2081					};
2082				};
2083
2084				port@1 {
2085					reg = < 0x01 >;
2086
2087					endpoint {
2088						remote-endpoint = < 0x5f >;
2089						phandle = < 0x5d >;
2090					};
2091				};
2092			};
2093
2094			in-ports {
2095
2096				port {
2097
2098					endpoint {
2099						remote-endpoint = < 0x60 >;
2100						phandle = < 0x65 >;
2101					};
2102				};
2103			};
2104		};
2105
2106		funnel@1a04000 {
2107			compatible = "arm,coresight-funnel\0arm,primecell";
2108			reg = < 0x1a04000 0x1000 >;
2109			clocks = < 0x12 0x08 >;
2110			clock-names = "apb_pclk";
2111
2112			in-ports {
2113				#address-cells = < 0x01 >;
2114				#size-cells = < 0x00 >;
2115
2116				port@0 {
2117					reg = < 0x00 >;
2118
2119					endpoint {
2120						remote-endpoint = < 0x61 >;
2121						phandle = < 0x67 >;
2122					};
2123				};
2124
2125				port@1 {
2126					reg = < 0x01 >;
2127
2128					endpoint {
2129						remote-endpoint = < 0x62 >;
2130						phandle = < 0x69 >;
2131					};
2132				};
2133
2134				port@4 {
2135					reg = < 0x04 >;
2136
2137					endpoint {
2138						remote-endpoint = < 0x63 >;
2139						phandle = < 0x6b >;
2140					};
2141				};
2142
2143				port@5 {
2144					reg = < 0x05 >;
2145
2146					endpoint {
2147						remote-endpoint = < 0x64 >;
2148						phandle = < 0x6d >;
2149					};
2150				};
2151			};
2152
2153			out-ports {
2154
2155				port {
2156
2157					endpoint {
2158						remote-endpoint = < 0x65 >;
2159						phandle = < 0x60 >;
2160					};
2161				};
2162			};
2163		};
2164
2165		etm@1a1c000 {
2166			compatible = "arm,coresight-etm3x\0arm,primecell";
2167			reg = < 0x1a1c000 0x1000 >;
2168			clocks = < 0x12 0x08 >;
2169			clock-names = "apb_pclk";
2170			cpu = < 0x66 >;
2171
2172			out-ports {
2173
2174				port {
2175
2176					endpoint {
2177						remote-endpoint = < 0x67 >;
2178						phandle = < 0x61 >;
2179					};
2180				};
2181			};
2182		};
2183
2184		etm@1a1d000 {
2185			compatible = "arm,coresight-etm3x\0arm,primecell";
2186			reg = < 0x1a1d000 0x1000 >;
2187			clocks = < 0x12 0x08 >;
2188			clock-names = "apb_pclk";
2189			cpu = < 0x68 >;
2190
2191			out-ports {
2192
2193				port {
2194
2195					endpoint {
2196						remote-endpoint = < 0x69 >;
2197						phandle = < 0x62 >;
2198					};
2199				};
2200			};
2201		};
2202
2203		etm@1a1e000 {
2204			compatible = "arm,coresight-etm3x\0arm,primecell";
2205			reg = < 0x1a1e000 0x1000 >;
2206			clocks = < 0x12 0x08 >;
2207			clock-names = "apb_pclk";
2208			cpu = < 0x6a >;
2209
2210			out-ports {
2211
2212				port {
2213
2214					endpoint {
2215						remote-endpoint = < 0x6b >;
2216						phandle = < 0x63 >;
2217					};
2218				};
2219			};
2220		};
2221
2222		etm@1a1f000 {
2223			compatible = "arm,coresight-etm3x\0arm,primecell";
2224			reg = < 0x1a1f000 0x1000 >;
2225			clocks = < 0x12 0x08 >;
2226			clock-names = "apb_pclk";
2227			cpu = < 0x6c >;
2228
2229			out-ports {
2230
2231				port {
2232
2233					endpoint {
2234						remote-endpoint = < 0x6d >;
2235						phandle = < 0x64 >;
2236					};
2237				};
2238			};
2239		};
2240
2241		regulator-fixed@1 {
2242			compatible = "regulator-fixed";
2243			regulator-min-microvolt = < 0x325aa0 >;
2244			regulator-max-microvolt = < 0x325aa0 >;
2245			regulator-name = "ext_3p3v";
2246			regulator-type = "voltage";
2247			startup-delay-us = < 0x00 >;
2248			gpio = < 0x20 0x4d 0x00 >;
2249			enable-active-high;
2250			regulator-boot-on;
2251			phandle = < 0x41 >;
2252		};
2253	};
2254
2255	pwrseq {
2256		compatible = "simple-bus";
2257
2258		sdcc4_pwrseq {
2259			pinctrl-names = "default";
2260			pinctrl-0 = < 0x6e >;
2261			compatible = "mmc-pwrseq-simple";
2262			reset-gpios = < 0x6f 0x2b 0x01 >;
2263			phandle = < 0x43 >;
2264		};
2265	};
2266
2267	leds {
2268		compatible = "gpio-leds";
2269		pinctrl-names = "default";
2270		pinctrl-0 = < 0x70 >;
2271
2272		led@1 {
2273			label = "apq8064:green:user1";
2274			gpios = < 0x6f 0x12 0x00 >;
2275			default-state = "on";
2276		};
2277	};
2278
2279	hdmi-out {
2280		compatible = "hdmi-connector";
2281		type = [ 64 00 ];
2282
2283		port {
2284
2285			endpoint {
2286				remote-endpoint = < 0x71 >;
2287				phandle = < 0x50 >;
2288			};
2289		};
2290	};
2291};
2292