1/* SPDX-License-Identifier: SHL-0.51 */
2
3/* Copyright 2018 ETH Zurich and University of Bologna.
4 * Copyright and related rights are licensed under the Solderpad Hardware
5 * License, Version 0.51 (the "License"); you may not use this file except in
6 * compliance with the License.  You may obtain a copy of the License at
7 * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
8 * or agreed to in writing, software, hardware and materials distributed under
9 * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
10 * CONDITIONS OF ANY KIND, either express or implied. See the License for the
11 * specific language governing permissions and limitations under the License.
12 */
13
14/dts-v1/;
15
16/ {
17  #address-cells = <2>;
18  #size-cells = <2>;
19  compatible = "eth,ariane-bare-dev";
20  model = "eth,ariane-bare";
21  chosen {
22  };
23  cpus {
24    #address-cells = <1>;
25    #size-cells = <0>;
26    timebase-frequency = <15000000>; // 15 MHz
27    CPU0: cpu@0 {
28      clock-frequency = <50000000>; // 50 MHz
29      device_type = "cpu";
30      reg = <0>;
31      status = "okay";
32      compatible = "eth, ariane", "riscv";
33      riscv,isa = "rv64imafdc";
34      mmu-type = "riscv,sv39";
35      tlb-split;
36      // HLIC - hart local interrupt controller
37      CPU0_intc: interrupt-controller {
38        #interrupt-cells = <1>;
39        interrupt-controller;
40        compatible = "riscv,cpu-intc";
41      };
42    };
43  };
44  memory@80000000 {
45    device_type = "memory";
46    reg = <0x0 0x80000000 0x0 0x40000000>;
47  };
48  leds {
49    compatible = "gpio-leds";
50    heartbeat-led {
51      gpios = <&xlnx_gpio 1 0>;
52      linux,default-trigger = "heartbeat";
53      retain-state-suspended;
54    };
55  };
56  L26: soc {
57    #address-cells = <2>;
58    #size-cells = <2>;
59    compatible = "eth,ariane-bare-soc", "simple-bus";
60    ranges;
61    clint@2000000 {
62      compatible = "riscv,clint0";
63      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
64      reg = <0x0 0x2000000 0x0 0xc0000>;
65      reg-names = "control";
66    };
67    PLIC0: interrupt-controller@c000000 {
68      #address-cells = <0>;
69      #interrupt-cells = <1>;
70      compatible = "riscv,plic0";
71      interrupt-controller;
72      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
73      reg = <0x0 0xc000000 0x0 0x4000000>;
74      riscv,max-priority = <7>;
75      riscv,ndev = <30>;
76    };
77    debug-controller@0 {
78      compatible = "riscv,debug-013";
79      interrupts-extended = <&CPU0_intc 65535>;
80      reg = <0x0 0x0 0x0 0x1000>;
81      reg-names = "control";
82    };
83    uart@10000000 {
84      compatible = "ns16750";
85      reg = <0x0 0x10000000 0x0 0x1000>;
86      clock-frequency = <50000000>;
87      current-speed = <115200>;
88      interrupt-parent = <&PLIC0>;
89      interrupts = <1>;
90      reg-shift = <2>; // regs are spaced on 32 bit boundary
91      reg-io-width = <4>; // only 32-bit access are supported
92    };
93    timer@18000000 {
94      compatible = "pulp,apb_timer";
95      interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>;
96      reg = <0x00000000 0x18000000 0x00000000 0x00001000>;
97      interrupt-parent = <&PLIC0>;
98      reg-names = "control";
99    };
100    xps-spi@20000000 {
101      compatible = "xlnx,xps-spi-2.00.b", "xlnx,xps-spi-2.00.a";
102      #address-cells = <1>;
103      #size-cells = <0>;
104      interrupt-parent = <&PLIC0>;
105      interrupts = < 2 2 >;
106      reg = < 0x0 0x20000000 0x0 0x1000 >;
107      xlnx,family = "kintex7";
108      xlnx,fifo-exist = <0x1>;
109      xlnx,num-ss-bits = <0x1>;
110      xlnx,num-transfer-bits = <0x8>;
111      xlnx,sck-ratio = <0x4>;
112
113      mmc@0 {
114        compatible = "mmc-spi-slot";
115        reg = <0>;
116        spi-max-frequency = <12500000>;
117        voltage-ranges = <3300 3300>;
118        disable-wp;
119      };
120
121      // mmc-slot@0 {
122      //   compatible = "fsl,mpc8323rdb-mmc-slot", "mmc-spi-slot";
123      //   reg = <0>;  //Chip select 0
124      //   spi-max-frequency = <12500000>;
125      //   voltage-ranges = <3300 3300>;
126      //   //interrupts = < 2 2 >;
127      //   //interrupt-parent = <&PLIC0>;
128      // };
129    };
130    eth: lowrisc-eth@30000000 {
131      compatible = "lowrisc-eth";
132      device_type = "network";
133      interrupt-parent = <&PLIC0>;
134      interrupts = <3 0>;
135      local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN
136      reg = <0x0 0x30000000 0x0 0x8000>;
137    };
138    xlnx_gpio: gpio@40000000 {
139      #gpio-cells = <2>;
140      compatible = "xlnx,xps-gpio-1.00.a";
141      gpio-controller ;
142      reg = <0x0 0x40000000 0x0 0x10000 >;
143      xlnx,all-inputs = <0x0>;
144      xlnx,all-inputs-2 = <0x0>;
145      xlnx,dout-default = <0x0>;
146      xlnx,dout-default-2 = <0x0>;
147      xlnx,gpio-width = <0x8>;
148      xlnx,gpio2-width = <0x8>;
149      xlnx,interrupt-present = <0x0>;
150      xlnx,is-dual = <0x1>;
151      xlnx,tri-default = <0xffffffff>;
152      xlnx,tri-default-2 = <0xffffffff>;
153    };
154  };
155};
156