1 /*
2 * cacheattr.c: MTRR and PAT initialisation.
3 *
4 * Copyright (c) 2008, Citrix Systems, Inc.
5 *
6 * Authors:
7 * Keir Fraser <keir@xen.org>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "util.h"
23 #include "config.h"
24
25 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
26 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
27 #define MSR_MTRRcap 0x00fe
28 #define MSR_MTRRfix64K_00000 0x0250
29 #define MSR_MTRRfix16K_80000 0x0258
30 #define MSR_MTRRfix16K_A0000 0x0259
31 #define MSR_MTRRfix4K_C0000 0x0268
32 #define MSR_MTRRfix4K_C8000 0x0269
33 #define MSR_MTRRfix4K_D0000 0x026a
34 #define MSR_MTRRfix4K_D8000 0x026b
35 #define MSR_MTRRfix4K_E0000 0x026c
36 #define MSR_MTRRfix4K_E8000 0x026d
37 #define MSR_MTRRfix4K_F0000 0x026e
38 #define MSR_MTRRfix4K_F8000 0x026f
39 #define MSR_PAT 0x0277
40 #define MSR_MTRRdefType 0x02ff
41
cpu_phys_addr(void)42 unsigned int cpu_phys_addr(void)
43 {
44 uint32_t eax, ebx, ecx, edx;
45 unsigned int phys_bits = 36;
46 /* Find the physical address size for this CPU. */
47 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
48 if ( eax >= 0x80000008 )
49 {
50 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
51 phys_bits = (uint8_t)eax;
52 }
53
54 return phys_bits;
55 }
56
cacheattr_init(void)57 void cacheattr_init(void)
58 {
59 uint32_t eax, ebx, ecx, edx;
60 uint64_t mtrr_cap, mtrr_def, content, addr_mask;
61 unsigned int i, nr_var_ranges, phys_bits;
62
63 /* Does the CPU support architectural MTRRs? */
64 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
65 if ( !(edx & (1u << 12)) )
66 return;
67
68 phys_bits = cpu_phys_addr();
69
70 printf("%u-bit phys ... ", phys_bits);
71
72 addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1);
73 mtrr_cap = rdmsr(MSR_MTRRcap);
74 mtrr_def = (1u << 11) | 6; /* E, default type WB */
75
76 /* Fixed-range MTRRs supported? */
77 if ( mtrr_cap & (1u << 8) )
78 {
79 /* 0x00000-0x9ffff: Write Back (WB) */
80 content = 0x0606060606060606ull;
81 wrmsr(MSR_MTRRfix64K_00000, content);
82 wrmsr(MSR_MTRRfix16K_80000, content);
83 /* 0xa0000-0xbffff: Write Combining (WC) */
84 if ( mtrr_cap & (1u << 10) ) /* WC supported? */
85 content = 0x0101010101010101ull;
86 wrmsr(MSR_MTRRfix16K_A0000, content);
87 /* 0xc0000-0xfffff: Write Back (WB) */
88 content = 0x0606060606060606ull;
89 for ( i = 0; i < 8; i++ )
90 wrmsr(MSR_MTRRfix4K_C0000 + i, content);
91 mtrr_def |= 1u << 10; /* FE */
92 printf("fixed MTRRs ... ");
93 }
94
95 /* Variable-range MTRRs supported? */
96 nr_var_ranges = (uint8_t)mtrr_cap;
97 if ( nr_var_ranges != 0 )
98 {
99 uint64_t base = pci_mem_start, size;
100
101 for ( i = 0; !(base >> 32) && (i < nr_var_ranges); i++ )
102 {
103 size = PAGE_SIZE;
104 while ( !(base & size) )
105 size <<= 1;
106 while ( ((base + size) < base) || ((base + size - 1) >> 32) )
107 size >>= 1;
108
109 wrmsr(MSR_MTRRphysBase(i), base);
110 wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
111
112 base += size;
113 }
114
115 for ( base = pci_hi_mem_start;
116 (base != pci_hi_mem_end) && (i < nr_var_ranges); i++ )
117 {
118 size = PAGE_SIZE;
119 while ( !(base & size) )
120 size <<= 1;
121 while ( (base + size < base) || (base + size > pci_hi_mem_end) )
122 size >>= 1;
123
124 wrmsr(MSR_MTRRphysBase(i), base);
125 wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
126
127 base += size;
128 }
129
130 printf("var MTRRs [%d/%d] ... ", i, nr_var_ranges);
131 }
132
133 wrmsr(MSR_MTRRdefType, mtrr_def);
134 }
135
136 /*
137 * Local variables:
138 * mode: C
139 * c-file-style: "BSD"
140 * c-basic-offset: 4
141 * tab-width: 4
142 * indent-tabs-mode: nil
143 * End:
144 */
145