1 #include <xen/init.h>
2 #include <xen/bitops.h>
3 #include <xen/mm.h>
4 #include <xen/smp.h>
5 #include <xen/pci.h>
6 #include <asm/io.h>
7 #include <asm/msr.h>
8 #include <asm/processor.h>
9 #include <asm/amd.h>
10 #include <asm/hvm/support.h>
11 #include <asm/setup.h> /* amd_init_cpu */
12 #include <asm/acpi.h>
13 #include <asm/apic.h>
14
15 #include "cpu.h"
16
17 /*
18 * Pre-canned values for overriding the CPUID features
19 * and extended features masks.
20 *
21 * Currently supported processors:
22 *
23 * "fam_0f_rev_c"
24 * "fam_0f_rev_d"
25 * "fam_0f_rev_e"
26 * "fam_0f_rev_f"
27 * "fam_0f_rev_g"
28 * "fam_10_rev_b"
29 * "fam_10_rev_c"
30 * "fam_11_rev_b"
31 */
32 static char __initdata opt_famrev[14];
33 string_param("cpuid_mask_cpu", opt_famrev);
34
35 static unsigned int __initdata opt_cpuid_mask_l7s0_eax = ~0u;
36 integer_param("cpuid_mask_l7s0_eax", opt_cpuid_mask_l7s0_eax);
37 static unsigned int __initdata opt_cpuid_mask_l7s0_ebx = ~0u;
38 integer_param("cpuid_mask_l7s0_ebx", opt_cpuid_mask_l7s0_ebx);
39
40 static unsigned int __initdata opt_cpuid_mask_thermal_ecx = ~0u;
41 integer_param("cpuid_mask_thermal_ecx", opt_cpuid_mask_thermal_ecx);
42
43 /* 1 = allow, 0 = don't allow guest creation, -1 = don't allow boot */
44 s8 __read_mostly opt_allow_unsafe;
45 boolean_param("allow_unsafe", opt_allow_unsafe);
46
rdmsr_amd_safe(unsigned int msr,unsigned int * lo,unsigned int * hi)47 static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
48 unsigned int *hi)
49 {
50 int err;
51
52 asm volatile("1: rdmsr\n2:\n"
53 ".section .fixup,\"ax\"\n"
54 "3: movl %6,%2\n"
55 " jmp 2b\n"
56 ".previous\n"
57 _ASM_EXTABLE(1b, 3b)
58 : "=a" (*lo), "=d" (*hi), "=r" (err)
59 : "c" (msr), "D" (0x9c5a203a), "2" (0), "i" (-EFAULT));
60
61 return err;
62 }
63
wrmsr_amd_safe(unsigned int msr,unsigned int lo,unsigned int hi)64 static inline int wrmsr_amd_safe(unsigned int msr, unsigned int lo,
65 unsigned int hi)
66 {
67 int err;
68
69 asm volatile("1: wrmsr\n2:\n"
70 ".section .fixup,\"ax\"\n"
71 "3: movl %6,%0\n"
72 " jmp 2b\n"
73 ".previous\n"
74 _ASM_EXTABLE(1b, 3b)
75 : "=r" (err)
76 : "c" (msr), "a" (lo), "d" (hi), "D" (0x9c5a203a),
77 "0" (0), "i" (-EFAULT));
78
79 return err;
80 }
81
wrmsr_amd(unsigned int msr,uint64_t val)82 static void wrmsr_amd(unsigned int msr, uint64_t val)
83 {
84 asm volatile("wrmsr" ::
85 "c" (msr), "a" ((uint32_t)val),
86 "d" (val >> 32), "D" (0x9c5a203a));
87 }
88
89 static const struct cpuidmask {
90 uint16_t fam;
91 char rev[2];
92 unsigned int ecx, edx, ext_ecx, ext_edx;
93 } pre_canned[] __initconst = {
94 #define CAN(fam, id, rev) { \
95 fam, #rev, \
96 AMD_FEATURES_##id##_REV_##rev##_ECX, \
97 AMD_FEATURES_##id##_REV_##rev##_EDX, \
98 AMD_EXTFEATURES_##id##_REV_##rev##_ECX, \
99 AMD_EXTFEATURES_##id##_REV_##rev##_EDX \
100 }
101 #define CAN_FAM(fam, rev) CAN(0x##fam, FAM##fam##h, rev)
102 #define CAN_K8(rev) CAN(0x0f, K8, rev)
103 CAN_FAM(11, B),
104 CAN_FAM(10, C),
105 CAN_FAM(10, B),
106 CAN_K8(G),
107 CAN_K8(F),
108 CAN_K8(E),
109 CAN_K8(D),
110 CAN_K8(C)
111 #undef CAN
112 };
113
get_cpuidmask(const char * opt)114 static const struct cpuidmask *__init noinline get_cpuidmask(const char *opt)
115 {
116 unsigned long fam;
117 char rev;
118 unsigned int i;
119
120 if (strncmp(opt, "fam_", 4))
121 return NULL;
122 fam = simple_strtoul(opt + 4, &opt, 16);
123 if (strncmp(opt, "_rev_", 5) || !opt[5] || opt[6])
124 return NULL;
125 rev = toupper(opt[5]);
126
127 for (i = 0; i < ARRAY_SIZE(pre_canned); ++i)
128 if (fam == pre_canned[i].fam && rev == *pre_canned[i].rev)
129 return &pre_canned[i];
130
131 return NULL;
132 }
133
134 /*
135 * Sets caps in expected_levelling_cap, probes for the specified mask MSR, and
136 * set caps in levelling_caps if it is found. Processors prior to Fam 10h
137 * required a 32-bit password for masking MSRs. Returns the default value.
138 */
_probe_mask_msr(unsigned int msr,uint64_t caps)139 static uint64_t __init _probe_mask_msr(unsigned int msr, uint64_t caps)
140 {
141 unsigned int hi, lo;
142
143 expected_levelling_cap |= caps;
144
145 if ((rdmsr_amd_safe(msr, &lo, &hi) == 0) &&
146 (wrmsr_amd_safe(msr, lo, hi) == 0))
147 levelling_caps |= caps;
148
149 return ((uint64_t)hi << 32) | lo;
150 }
151
152 /*
153 * Probe for the existance of the expected masking MSRs. They might easily
154 * not be available if Xen is running virtualised.
155 */
probe_masking_msrs(void)156 static void __init noinline probe_masking_msrs(void)
157 {
158 const struct cpuinfo_x86 *c = &boot_cpu_data;
159
160 /*
161 * First, work out which masking MSRs we should have, based on
162 * revision and cpuid.
163 */
164
165 /* Fam11 doesn't support masking at all. */
166 if (c->x86 == 0x11)
167 return;
168
169 cpuidmask_defaults._1cd =
170 _probe_mask_msr(MSR_K8_FEATURE_MASK, LCAP_1cd);
171 cpuidmask_defaults.e1cd =
172 _probe_mask_msr(MSR_K8_EXT_FEATURE_MASK, LCAP_e1cd);
173
174 if (c->cpuid_level >= 7)
175 cpuidmask_defaults._7ab0 =
176 _probe_mask_msr(MSR_AMD_L7S0_FEATURE_MASK, LCAP_7ab0);
177
178 if (c->x86 == 0x15 && c->cpuid_level >= 6 && cpuid_ecx(6))
179 cpuidmask_defaults._6c =
180 _probe_mask_msr(MSR_AMD_THRM_FEATURE_MASK, LCAP_6c);
181
182 /*
183 * Don't bother warning about a mismatch if virtualised. These MSRs
184 * are not architectural and almost never virtualised.
185 */
186 if ((expected_levelling_cap == levelling_caps) ||
187 cpu_has_hypervisor)
188 return;
189
190 printk(XENLOG_WARNING "Mismatch between expected (%#x) "
191 "and real (%#x) levelling caps: missing %#x\n",
192 expected_levelling_cap, levelling_caps,
193 (expected_levelling_cap ^ levelling_caps) & levelling_caps);
194 printk(XENLOG_WARNING "Fam %#x, model %#x level %#x\n",
195 c->x86, c->x86_model, c->cpuid_level);
196 printk(XENLOG_WARNING
197 "If not running virtualised, please report a bug\n");
198 }
199
200 /*
201 * Context switch CPUID masking state to the next domain. Only called if
202 * CPUID Faulting isn't available, but masking MSRs have been detected. A
203 * parameter of NULL is used to context switch to the default host state (by
204 * the cpu bringup-code, crash path, etc).
205 */
amd_ctxt_switch_masking(const struct vcpu * next)206 static void amd_ctxt_switch_masking(const struct vcpu *next)
207 {
208 struct cpuidmasks *these_masks = &this_cpu(cpuidmasks);
209 const struct domain *nextd = next ? next->domain : NULL;
210 const struct cpuidmasks *masks =
211 (nextd && is_pv_domain(nextd) && nextd->arch.pv_domain.cpuidmasks)
212 ? nextd->arch.pv_domain.cpuidmasks : &cpuidmask_defaults;
213
214 if ((levelling_caps & LCAP_1cd) == LCAP_1cd) {
215 uint64_t val = masks->_1cd;
216
217 /*
218 * OSXSAVE defaults to 1, which causes fast-forwarding of
219 * Xen's real setting. Clobber it if disabled by the guest
220 * kernel.
221 */
222 if (next && is_pv_vcpu(next) && !is_idle_vcpu(next) &&
223 !(next->arch.pv_vcpu.ctrlreg[4] & X86_CR4_OSXSAVE))
224 val &= ~((uint64_t)cpufeat_mask(X86_FEATURE_OSXSAVE) << 32);
225
226 if (unlikely(these_masks->_1cd != val)) {
227 wrmsr_amd(MSR_K8_FEATURE_MASK, val);
228 these_masks->_1cd = val;
229 }
230 }
231
232 #define LAZY(cap, msr, field) \
233 ({ \
234 if (unlikely(these_masks->field != masks->field) && \
235 ((levelling_caps & cap) == cap)) \
236 { \
237 wrmsr_amd(msr, masks->field); \
238 these_masks->field = masks->field; \
239 } \
240 })
241
242 LAZY(LCAP_e1cd, MSR_K8_EXT_FEATURE_MASK, e1cd);
243 LAZY(LCAP_7ab0, MSR_AMD_L7S0_FEATURE_MASK, _7ab0);
244 LAZY(LCAP_6c, MSR_AMD_THRM_FEATURE_MASK, _6c);
245
246 #undef LAZY
247 }
248
249 /*
250 * Mask the features and extended features returned by CPUID. Parameters are
251 * set from the boot line via two methods:
252 *
253 * 1) Specific processor revision string
254 * 2) User-defined masks
255 *
256 * The user-defined masks take precedence.
257 *
258 * AMD "masking msrs" are actually overrides, making it possible to advertise
259 * features which are not supported by the hardware. Care must be taken to
260 * avoid this, as the accidentally-advertised features will not actually
261 * function.
262 */
amd_init_levelling(void)263 static void __init noinline amd_init_levelling(void)
264 {
265 const struct cpuidmask *m = NULL;
266
267 if (probe_cpuid_faulting())
268 return;
269
270 probe_masking_msrs();
271
272 if (*opt_famrev != '\0') {
273 m = get_cpuidmask(opt_famrev);
274
275 if (!m)
276 printk("Invalid processor string: %s\n", opt_famrev);
277 }
278
279 if ((levelling_caps & LCAP_1cd) == LCAP_1cd) {
280 uint32_t ecx, edx, tmp;
281
282 cpuid(0x00000001, &tmp, &tmp, &ecx, &edx);
283
284 if (~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx)) {
285 ecx &= opt_cpuid_mask_ecx;
286 edx &= opt_cpuid_mask_edx;
287 } else if (m) {
288 ecx &= m->ecx;
289 edx &= m->edx;
290 }
291
292 /* Fast-forward bits - Must be set. */
293 if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
294 ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
295 edx |= cpufeat_mask(X86_FEATURE_APIC);
296
297 /* Allow the HYPERVISOR bit to be set via guest policy. */
298 ecx |= cpufeat_mask(X86_FEATURE_HYPERVISOR);
299
300 cpuidmask_defaults._1cd = ((uint64_t)ecx << 32) | edx;
301 }
302
303 if ((levelling_caps & LCAP_e1cd) == LCAP_e1cd) {
304 uint32_t ecx, edx, tmp;
305
306 cpuid(0x80000001, &tmp, &tmp, &ecx, &edx);
307
308 if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) {
309 ecx &= opt_cpuid_mask_ext_ecx;
310 edx &= opt_cpuid_mask_ext_edx;
311 } else if (m) {
312 ecx &= m->ext_ecx;
313 edx &= m->ext_edx;
314 }
315
316 /* Fast-forward bits - Must be set. */
317 edx |= cpufeat_mask(X86_FEATURE_APIC);
318
319 cpuidmask_defaults.e1cd = ((uint64_t)ecx << 32) | edx;
320 }
321
322 if ((levelling_caps & LCAP_7ab0) == LCAP_7ab0) {
323 uint32_t eax, ebx, tmp;
324
325 cpuid(0x00000007, &eax, &ebx, &tmp, &tmp);
326
327 if (~(opt_cpuid_mask_l7s0_eax & opt_cpuid_mask_l7s0_ebx)) {
328 eax &= opt_cpuid_mask_l7s0_eax;
329 ebx &= opt_cpuid_mask_l7s0_ebx;
330 }
331
332 cpuidmask_defaults._7ab0 &= ((uint64_t)eax << 32) | ebx;
333 }
334
335 if ((levelling_caps & LCAP_6c) == LCAP_6c) {
336 uint32_t ecx = cpuid_ecx(6);
337
338 if (~opt_cpuid_mask_thermal_ecx)
339 ecx &= opt_cpuid_mask_thermal_ecx;
340
341 cpuidmask_defaults._6c &= (~0ULL << 32) | ecx;
342 }
343
344 if (opt_cpu_info) {
345 printk(XENLOG_INFO "Levelling caps: %#x\n", levelling_caps);
346 printk(XENLOG_INFO
347 "MSR defaults: 1d 0x%08x, 1c 0x%08x, e1d 0x%08x, "
348 "e1c 0x%08x, 7a0 0x%08x, 7b0 0x%08x, 6c 0x%08x\n",
349 (uint32_t)cpuidmask_defaults._1cd,
350 (uint32_t)(cpuidmask_defaults._1cd >> 32),
351 (uint32_t)cpuidmask_defaults.e1cd,
352 (uint32_t)(cpuidmask_defaults.e1cd >> 32),
353 (uint32_t)(cpuidmask_defaults._7ab0 >> 32),
354 (uint32_t)cpuidmask_defaults._7ab0,
355 (uint32_t)cpuidmask_defaults._6c);
356 }
357
358 if (levelling_caps)
359 ctxt_switch_masking = amd_ctxt_switch_masking;
360 }
361
362 /*
363 * Check for the presence of an AMD erratum. Arguments are defined in amd.h
364 * for each known erratum. Return 1 if erratum is found.
365 */
cpu_has_amd_erratum(const struct cpuinfo_x86 * cpu,int osvw_id,...)366 int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...)
367 {
368 va_list ap;
369 u32 range;
370 u32 ms;
371
372 if (cpu->x86_vendor != X86_VENDOR_AMD)
373 return 0;
374
375 if (osvw_id >= 0 && cpu_has(cpu, X86_FEATURE_OSVW)) {
376 u64 osvw_len;
377
378 rdmsrl(MSR_AMD_OSVW_ID_LENGTH, osvw_len);
379
380 if (osvw_id < osvw_len) {
381 u64 osvw_bits;
382
383 rdmsrl(MSR_AMD_OSVW_STATUS + (osvw_id >> 6),
384 osvw_bits);
385
386 return (osvw_bits >> (osvw_id & 0x3f)) & 1;
387 }
388 }
389
390 /* OSVW unavailable or ID unknown, match family-model-stepping range */
391 va_start(ap, osvw_id);
392
393 ms = (cpu->x86_model << 4) | cpu->x86_mask;
394 while ((range = va_arg(ap, int))) {
395 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
396 (ms >= AMD_MODEL_RANGE_START(range)) &&
397 (ms <= AMD_MODEL_RANGE_END(range))) {
398 va_end(ap);
399 return 1;
400 }
401 }
402
403 va_end(ap);
404 return 0;
405 }
406
407 /*
408 * Disable C1-Clock ramping if enabled in PMM7.CpuLowPwrEnh on 8th-generation
409 * cores only. Assume BIOS has setup all Northbridges equivalently.
410 */
disable_c1_ramping(void)411 static void disable_c1_ramping(void)
412 {
413 u8 pmm7;
414 int node, nr_nodes;
415
416 /* Read the number of nodes from the first Northbridge. */
417 nr_nodes = ((pci_conf_read32(0, 0, 0x18, 0x0, 0x60)>>4)&0x07)+1;
418 for (node = 0; node < nr_nodes; node++) {
419 /* PMM7: bus=0, dev=0x18+node, function=0x3, register=0x87. */
420 pmm7 = pci_conf_read8(0, 0, 0x18+node, 0x3, 0x87);
421 /* Invalid read means we've updated every Northbridge. */
422 if (pmm7 == 0xFF)
423 break;
424 pmm7 &= 0xFC; /* clear pmm7[1:0] */
425 pci_conf_write8(0, 0, 0x18+node, 0x3, 0x87, pmm7);
426 printk ("AMD: Disabling C1 Clock Ramping Node #%x\n", node);
427 }
428 }
429
disable_c1e(void * unused)430 static void disable_c1e(void *unused)
431 {
432 uint64_t msr_content;
433
434 /*
435 * Disable C1E mode, as the APIC timer stops in that mode.
436 * The MSR does not exist in all FamilyF CPUs (only Rev F and above),
437 * but we safely catch the #GP in that case.
438 */
439 if ((rdmsr_safe(MSR_K8_ENABLE_C1E, msr_content) == 0) &&
440 (msr_content & (3ULL << 27)) &&
441 (wrmsr_safe(MSR_K8_ENABLE_C1E, msr_content & ~(3ULL << 27)) != 0))
442 printk(KERN_ERR "Failed to disable C1E on CPU#%u (%16"PRIx64")\n",
443 smp_processor_id(), msr_content);
444 }
445
check_disable_c1e(unsigned int port,u8 value)446 static void check_disable_c1e(unsigned int port, u8 value)
447 {
448 /* C1E is sometimes enabled during entry to ACPI mode. */
449 if ((port == acpi_smi_cmd) && (value == acpi_enable_value))
450 on_each_cpu(disable_c1e, NULL, 1);
451 }
452
453 /*
454 * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG :
455 * "The MtrrFixDramModEn bit should be set to 1 during BIOS initalization of
456 * the fixed MTRRs, then cleared to 0 for operation."
457 */
check_syscfg_dram_mod_en(void)458 static void check_syscfg_dram_mod_en(void)
459 {
460 uint64_t syscfg;
461 static bool_t printed = 0;
462
463 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
464 (boot_cpu_data.x86 >= 0x0f)))
465 return;
466
467 rdmsrl(MSR_K8_SYSCFG, syscfg);
468 if (!(syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY))
469 return;
470
471 if (!test_and_set_bool(printed))
472 printk(KERN_ERR "MTRR: SYSCFG[MtrrFixDramModEn] not "
473 "cleared by BIOS, clearing this bit\n");
474
475 syscfg &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
476 wrmsrl(MSR_K8_SYSCFG, syscfg);
477 }
478
amd_get_topology(struct cpuinfo_x86 * c)479 static void amd_get_topology(struct cpuinfo_x86 *c)
480 {
481 int cpu;
482 unsigned bits;
483
484 if (c->x86_max_cores <= 1)
485 return;
486 /*
487 * On a AMD multi core setup the lower bits of the APIC id
488 * distingush the cores.
489 */
490 cpu = smp_processor_id();
491 bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
492
493 if (bits == 0) {
494 while ((1 << bits) < c->x86_max_cores)
495 bits++;
496 }
497
498 /* Low order bits define the core id */
499 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
500 /* Convert local APIC ID into the socket ID */
501 c->phys_proc_id >>= bits;
502 /* Collect compute unit ID if available */
503 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
504 u32 eax, ebx, ecx, edx;
505
506 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
507 c->compute_unit_id = ebx & 0xFF;
508 c->x86_num_siblings = ((ebx >> 8) & 0x3) + 1;
509 }
510
511 if (opt_cpu_info)
512 printk("CPU %d(%d) -> Processor %d, %s %d\n",
513 cpu, c->x86_max_cores, c->phys_proc_id,
514 cpu_has(c, X86_FEATURE_TOPOEXT) ? "Compute Unit" :
515 "Core",
516 cpu_has(c, X86_FEATURE_TOPOEXT) ? c->compute_unit_id :
517 c->cpu_core_id);
518 }
519
early_init_amd(struct cpuinfo_x86 * c)520 static void early_init_amd(struct cpuinfo_x86 *c)
521 {
522 if (c == &boot_cpu_data)
523 amd_init_levelling();
524
525 ctxt_switch_levelling(NULL);
526 }
527
init_amd(struct cpuinfo_x86 * c)528 static void init_amd(struct cpuinfo_x86 *c)
529 {
530 u32 l, h;
531
532 unsigned long long value;
533
534 /* Disable TLB flush filter by setting HWCR.FFDIS on K8
535 * bit 6 of msr C001_0015
536 *
537 * Errata 63 for SH-B3 steppings
538 * Errata 122 for all steppings (F+ have it disabled by default)
539 */
540 if (c->x86 == 15) {
541 rdmsrl(MSR_K7_HWCR, value);
542 value |= 1 << 6;
543 wrmsrl(MSR_K7_HWCR, value);
544 }
545
546 /*
547 * Some AMD CPUs duplicate the 3DNow bit in base and extended CPUID
548 * leaves. Unfortunately, this aliases PBE on Intel CPUs. Clobber the
549 * alias, leaving 3DNow in the extended leaf.
550 */
551 __clear_bit(X86_FEATURE_PBE, c->x86_capability);
552
553 if (c->x86 == 0xf && c->x86_model < 0x14
554 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
555 /*
556 * Some BIOSes incorrectly force this feature, but only K8
557 * revision D (model = 0x14) and later actually support it.
558 * (AMD Erratum #110, docId: 25759).
559 */
560 __clear_bit(X86_FEATURE_LAHF_LM, c->x86_capability);
561 if (!rdmsr_amd_safe(0xc001100d, &l, &h))
562 wrmsr_amd_safe(0xc001100d, l, h & ~1);
563 }
564
565 /* MFENCE stops RDTSC speculation */
566 __set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
567
568 switch(c->x86)
569 {
570 case 0xf ... 0x17:
571 disable_c1e(NULL);
572 if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
573 pv_post_outb_hook = check_disable_c1e;
574 break;
575 }
576
577 display_cacheinfo(c);
578
579 if (c->extended_cpuid_level >= 0x80000008) {
580 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
581 }
582
583 if (c->extended_cpuid_level >= 0x80000007) {
584 if (cpu_has(c, X86_FEATURE_ITSC)) {
585 __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
586 __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
587 if (c->x86 != 0x11)
588 __set_bit(X86_FEATURE_TSC_RELIABLE,
589 c->x86_capability);
590 }
591 }
592
593 /* re-enable TopologyExtensions if switched off by BIOS */
594 if ((c->x86 == 0x15) &&
595 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
596 !cpu_has(c, X86_FEATURE_TOPOEXT) &&
597 !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, value)) {
598 value |= 1ULL << 54;
599 wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, value);
600 rdmsrl(MSR_K8_EXT_FEATURE_MASK, value);
601 if (value & (1ULL << 54)) {
602 __set_bit(X86_FEATURE_TOPOEXT, c->x86_capability);
603 printk(KERN_INFO "CPU: Re-enabling disabled "
604 "Topology Extensions Support\n");
605 }
606 }
607
608 /*
609 * The way access filter has a performance penalty on some workloads.
610 * Disable it on the affected CPUs.
611 */
612 if (c->x86 == 0x15 && c->x86_model >= 0x02 && c->x86_model < 0x20 &&
613 !rdmsr_safe(MSR_AMD64_IC_CFG, value) && (value & 0x1e) != 0x1e)
614 wrmsr_safe(MSR_AMD64_IC_CFG, value | 0x1e);
615
616 amd_get_topology(c);
617
618 /* Pointless to use MWAIT on Family10 as it does not deep sleep. */
619 if (c->x86 == 0x10)
620 __clear_bit(X86_FEATURE_MONITOR, c->x86_capability);
621
622 if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121))
623 opt_allow_unsafe = 1;
624 else if (opt_allow_unsafe < 0)
625 panic("Xen will not boot on this CPU for security reasons"
626 "Pass \"allow_unsafe\" if you're trusting all your"
627 " (PV) guest kernels.\n");
628 else if (!opt_allow_unsafe && c == &boot_cpu_data)
629 printk(KERN_WARNING
630 "*** Xen will not allow creation of DomU-s on"
631 " this CPU for security reasons. ***\n"
632 KERN_WARNING
633 "*** Pass \"allow_unsafe\" if you're trusting"
634 " all your (PV) guest kernels. ***\n");
635
636 if (c->x86 == 0x16 && c->x86_model <= 0xf) {
637 if (c == &boot_cpu_data) {
638 l = pci_conf_read32(0, 0, 0x18, 0x3, 0x58);
639 h = pci_conf_read32(0, 0, 0x18, 0x3, 0x5c);
640 if ((l & 0x1f) | (h & 0x1))
641 printk(KERN_WARNING
642 "Applying workaround for erratum 792: %s%s%s\n",
643 (l & 0x1f) ? "clearing D18F3x58[4:0]" : "",
644 ((l & 0x1f) && (h & 0x1)) ? " and " : "",
645 (h & 0x1) ? "clearing D18F3x5C[0]" : "");
646
647 if (l & 0x1f)
648 pci_conf_write32(0, 0, 0x18, 0x3, 0x58,
649 l & ~0x1f);
650
651 if (h & 0x1)
652 pci_conf_write32(0, 0, 0x18, 0x3, 0x5c,
653 h & ~0x1);
654 }
655
656 rdmsrl(MSR_AMD64_LS_CFG, value);
657 if (!(value & (1 << 15))) {
658 static bool_t warned;
659
660 if (c == &boot_cpu_data || opt_cpu_info ||
661 !test_and_set_bool(warned))
662 printk(KERN_WARNING
663 "CPU%u: Applying workaround for erratum 793\n",
664 smp_processor_id());
665 wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
666 }
667 } else if (c->x86 == 0x12) {
668 rdmsrl(MSR_AMD64_DE_CFG, value);
669 if (!(value & (1U << 31))) {
670 static bool warned;
671
672 if (c == &boot_cpu_data || opt_cpu_info ||
673 !test_and_set_bool(warned))
674 printk(KERN_WARNING
675 "CPU%u: Applying workaround for erratum 665\n",
676 smp_processor_id());
677 wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
678 }
679 }
680
681 /* AMD CPUs do not support SYSENTER outside of legacy mode. */
682 __clear_bit(X86_FEATURE_SEP, c->x86_capability);
683
684 if (c->x86 == 0x10) {
685 /* do this for boot cpu */
686 if (c == &boot_cpu_data)
687 check_enable_amd_mmconf_dmi();
688
689 fam10h_check_enable_mmcfg();
690
691 /*
692 * On family 10h BIOS may not have properly enabled WC+
693 * support, causing it to be converted to CD memtype. This may
694 * result in performance degradation for certain nested-paging
695 * guests. Prevent this conversion by clearing bit 24 in
696 * MSR_F10_BU_CFG2.
697 */
698 rdmsrl(MSR_F10_BU_CFG2, value);
699 value &= ~(1ULL << 24);
700 wrmsrl(MSR_F10_BU_CFG2, value);
701 }
702
703 /*
704 * Family 0x12 and above processors have APIC timer
705 * running in deep C states.
706 */
707 if ( opt_arat && c->x86 > 0x11 )
708 __set_bit(X86_FEATURE_ARAT, c->x86_capability);
709
710 /*
711 * Prior to Family 0x14, perf counters are not reset during warm reboot.
712 * We have to reset them manually.
713 */
714 if (nmi_watchdog != NMI_LOCAL_APIC && c->x86 < 0x14) {
715 wrmsrl(MSR_K7_PERFCTR0, 0);
716 wrmsrl(MSR_K7_PERFCTR1, 0);
717 wrmsrl(MSR_K7_PERFCTR2, 0);
718 wrmsrl(MSR_K7_PERFCTR3, 0);
719 }
720
721 if (cpu_has(c, X86_FEATURE_EFRO)) {
722 rdmsr(MSR_K7_HWCR, l, h);
723 l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
724 wrmsr(MSR_K7_HWCR, l, h);
725 }
726
727 /* Prevent TSC drift in non single-processor, single-core platforms. */
728 if ((smp_processor_id() == 1) && !cpu_has(c, X86_FEATURE_ITSC))
729 disable_c1_ramping();
730
731 check_syscfg_dram_mod_en();
732 }
733
734 static const struct cpu_dev amd_cpu_dev = {
735 .c_vendor = "AMD",
736 .c_ident = { "AuthenticAMD" },
737 .c_early_init = early_init_amd,
738 .c_init = init_amd,
739 };
740
amd_init_cpu(void)741 int __init amd_init_cpu(void)
742 {
743 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
744 return 0;
745 }
746