1 #include <xen/irq.h> 2 #include <xen/sched.h> 3 #include <asm/current.h> 4 #include <asm/smp.h> 5 #include <asm/hardirq.h> 6 #include <mach_apic.h> 7 8 target_cpus_all(void)9const cpumask_t *target_cpus_all(void) 10 { 11 return &cpu_online_map; 12 } 13 14 /* 15 * LOGICAL FLAT DELIVERY MODE (multicast via bitmask to <= 8 logical APIC IDs). 16 */ 17 init_apic_ldr_flat(void)18void init_apic_ldr_flat(void) 19 { 20 unsigned long val; 21 22 apic_write(APIC_DFR, APIC_DFR_FLAT); 23 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 24 val |= SET_xAPIC_LOGICAL_ID(1UL << smp_processor_id()); 25 apic_write(APIC_LDR, val); 26 } 27 clustered_apic_check_flat(void)28void __init clustered_apic_check_flat(void) 29 { 30 printk("Enabling APIC mode: Flat. Using %d I/O APICs\n", nr_ioapics); 31 } 32 vector_allocation_cpumask_flat(int cpu)33const cpumask_t *vector_allocation_cpumask_flat(int cpu) 34 { 35 return &cpu_online_map; 36 } 37 cpu_mask_to_apicid_flat(const cpumask_t * cpumask)38unsigned int cpu_mask_to_apicid_flat(const cpumask_t *cpumask) 39 { 40 return cpumask_bits(cpumask)[0]&0xFF; 41 } 42 43 /* 44 * PHYSICAL DELIVERY MODE (unicast to physical APIC IDs). 45 */ 46 init_apic_ldr_phys(void)47void init_apic_ldr_phys(void) 48 { 49 unsigned long val; 50 apic_write(APIC_DFR, APIC_DFR_FLAT); 51 /* A dummy logical ID should be fine. We only deliver in phys mode. */ 52 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 53 apic_write(APIC_LDR, val); 54 } 55 clustered_apic_check_phys(void)56void __init clustered_apic_check_phys(void) 57 { 58 printk("Enabling APIC mode: Phys. Using %d I/O APICs\n", nr_ioapics); 59 } 60 vector_allocation_cpumask_phys(int cpu)61const cpumask_t *vector_allocation_cpumask_phys(int cpu) 62 { 63 return cpumask_of(cpu); 64 } 65 cpu_mask_to_apicid_phys(const cpumask_t * cpumask)66unsigned int cpu_mask_to_apicid_phys(const cpumask_t *cpumask) 67 { 68 /* As we are using single CPU as destination, pick only one CPU here */ 69 return cpu_physical_id(cpumask_any(cpumask)); 70 } 71