1 /* 2 * ARM Generic Interrupt Controller v3 definitions 3 * 4 * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com> 5 * Copyright (c) 2014 Cavium Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __ASM_ARM_GIC_V3_DEFS_H__ 19 #define __ASM_ARM_GIC_V3_DEFS_H__ 20 21 /* 22 * Additional registers defined in GIC v3. 23 * Common GICD registers are defined in gic.h 24 */ 25 26 #define GICD_STATUSR (0x010) 27 #define GICD_SETSPI_NSR (0x040) 28 #define GICD_CLRSPI_NSR (0x048) 29 #define GICD_SETSPI_SR (0x050) 30 #define GICD_CLRSPI_SR (0x058) 31 #define GICD_IROUTER (0x6000) 32 #define GICD_IROUTER32 (0x6100) 33 #define GICD_IROUTER1019 (0x7FD8) 34 #define GICD_PIDR2 (0xFFE8) 35 36 /* Common between GICD_PIDR2 and GICR_PIDR2 */ 37 #define GIC_PIDR2_ARCH_MASK (0xf0) 38 #define GIC_PIDR2_ARCH_GICv3 (0x30) 39 #define GIC_PIDR2_ARCH_GICv4 (0x40) 40 41 #define GICC_SRE_EL2_SRE (1UL << 0) 42 #define GICC_SRE_EL2_DFB (1UL << 1) 43 #define GICC_SRE_EL2_DIB (1UL << 2) 44 #define GICC_SRE_EL2_ENEL1 (1UL << 3) 45 46 /* Additional bits in GICD_TYPER defined by GICv3 */ 47 #define GICD_TYPE_ID_BITS_SHIFT 19 48 #define GICD_TYPE_ID_BITS(r) ((((r) >> GICD_TYPE_ID_BITS_SHIFT) & 0x1f) + 1) 49 50 #define GICD_TYPE_LPIS (1U << 17) 51 52 #define GICD_CTLR_RWP (1UL << 31) 53 #define GICD_CTLR_ARE_NS (1U << 4) 54 #define GICD_CTLR_ENABLE_G1A (1U << 1) 55 #define GICD_CTLR_ENABLE_G1 (1U << 0) 56 #define GICD_IROUTER_SPI_MODE_ANY (1UL << 31) 57 58 #define GICC_CTLR_EL1_EOImode_drop (1U << 1) 59 60 #define GICR_WAKER_ProcessorSleep (1U << 1) 61 #define GICR_WAKER_ChildrenAsleep (1U << 2) 62 63 #define GICR_SYNCR_NOT_BUSY 1 64 /* 65 * Implementation defined value JEP106? 66 * use physical hw value for now 67 */ 68 #define GICV3_GICD_IIDR_VAL 0x34c 69 #define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL 70 71 #define GICR_CTLR (0x0000) 72 #define GICR_IIDR (0x0004) 73 #define GICR_TYPER (0x0008) 74 #define GICR_STATUSR (0x0010) 75 #define GICR_WAKER (0x0014) 76 #define GICR_SETLPIR (0x0040) 77 #define GICR_CLRLPIR (0x0048) 78 #define GICR_PROPBASER (0x0070) 79 #define GICR_PENDBASER (0x0078) 80 #define GICR_INVLPIR (0x00A0) 81 #define GICR_INVALLR (0x00B0) 82 #define GICR_SYNCR (0x00C0) 83 #define GICR_PIDR2 GICD_PIDR2 84 85 /* GICR for SGI's & PPI's */ 86 87 #define GICR_IGROUPR0 (0x0080) 88 #define GICR_ISENABLER0 (0x0100) 89 #define GICR_ICENABLER0 (0x0180) 90 #define GICR_ISPENDR0 (0x0200) 91 #define GICR_ICPENDR0 (0x0280) 92 #define GICR_ISACTIVER0 (0x0300) 93 #define GICR_ICACTIVER0 (0x0380) 94 #define GICR_IPRIORITYR0 (0x0400) 95 #define GICR_IPRIORITYR7 (0x041C) 96 #define GICR_ICFGR0 (0x0C00) 97 #define GICR_ICFGR1 (0x0C04) 98 #define GICR_IGRPMODR0 (0x0D00) 99 #define GICR_NSACR (0x0E00) 100 101 #define GICR_CTLR_ENABLE_LPIS (1U << 0) 102 103 #define GICR_TYPER_PLPIS (1U << 0) 104 #define GICR_TYPER_VLPIS (1U << 1) 105 #define GICR_TYPER_LAST (1U << 4) 106 #define GICR_TYPER_PROC_NUM_SHIFT 8 107 #define GICR_TYPER_PROC_NUM_MASK (0xffff << GICR_TYPER_PROC_NUM_SHIFT) 108 109 /* For specifying the inner cacheability type only */ 110 #define GIC_BASER_CACHE_nCnB 0ULL 111 /* For specifying the outer cacheability type only */ 112 #define GIC_BASER_CACHE_SameAsInner 0ULL 113 #define GIC_BASER_CACHE_nC 1ULL 114 #define GIC_BASER_CACHE_RaWt 2ULL 115 #define GIC_BASER_CACHE_RaWb 3ULL 116 #define GIC_BASER_CACHE_WaWt 4ULL 117 #define GIC_BASER_CACHE_WaWb 5ULL 118 #define GIC_BASER_CACHE_RaWaWt 6ULL 119 #define GIC_BASER_CACHE_RaWaWb 7ULL 120 #define GIC_BASER_CACHE_MASK 7ULL 121 122 #define GIC_BASER_NonShareable 0ULL 123 #define GIC_BASER_InnerShareable 1ULL 124 #define GIC_BASER_OuterShareable 2ULL 125 126 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 127 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ 128 (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) 129 #define GICR_PROPBASER_SHAREABILITY_SHIFT 10 130 #define GICR_PROPBASER_SHAREABILITY_MASK \ 131 (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) 132 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 133 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ 134 (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) 135 #define GICR_PROPBASER_RES0_MASK \ 136 (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) 137 138 #define GICR_PENDBASER_SHAREABILITY_SHIFT 10 139 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 140 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT 56 141 #define GICR_PENDBASER_SHAREABILITY_MASK \ 142 (3UL << GICR_PENDBASER_SHAREABILITY_SHIFT) 143 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ 144 (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) 145 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ 146 (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) 147 #define GICR_PENDBASER_PTZ BIT(62) 148 #define GICR_PENDBASER_RES0_MASK \ 149 (BIT(63) | GENMASK(61, 59) | GENMASK(55, 52) | \ 150 GENMASK(15, 12) | GENMASK(6, 0)) 151 152 #define DEFAULT_PMR_VALUE 0xff 153 154 #define LPI_PROP_PRIO_MASK 0xfc 155 #define LPI_PROP_RES1 (1 << 1) 156 #define LPI_PROP_ENABLED (1 << 0) 157 158 #define GICH_VMCR_EOI (1 << 9) 159 #define GICH_VMCR_VENG1 (1 << 1) 160 161 #define GICH_LR_VIRTUAL_MASK 0xffff 162 #define GICH_LR_VIRTUAL_SHIFT 0 163 #define GICH_LR_PHYSICAL_MASK 0x3ff 164 #define GICH_LR_PHYSICAL_SHIFT 32 165 #define GICH_LR_STATE_MASK 0x3 166 #define GICH_LR_STATE_SHIFT 62 167 #define GICH_LR_PRIORITY_MASK 0xff 168 #define GICH_LR_PRIORITY_SHIFT 48 169 #define GICH_LR_HW_MASK 0x1 170 #define GICH_LR_HW_SHIFT 61 171 #define GICH_LR_GRP_MASK 0x1 172 #define GICH_LR_GRP_SHIFT 60 173 #define GICH_LR_MAINTENANCE_IRQ (1UL<<41) 174 #define GICH_LR_GRP1 (1UL<<60) 175 #define GICH_LR_HW (1UL<<61) 176 177 #define GICH_VTR_NRLRGS 0x3f 178 #define GICH_VTR_PRIBITS_MASK 0x7 179 #define GICH_VTR_PRIBITS_SHIFT 29 180 181 #define GICH_VMCR_PRIORITY_MASK 0xff 182 #define GICH_VMCR_PRIORITY_SHIFT 24 183 184 #define ICH_SGI_IRQMODE_SHIFT 40 185 #define ICH_SGI_IRQMODE_MASK 0x1 186 #define ICH_SGI_TARGET_OTHERS 1UL 187 #define ICH_SGI_TARGET_LIST 0 188 #define ICH_SGI_IRQ_SHIFT 24 189 #define ICH_SGI_IRQ_MASK 0xf 190 #define ICH_SGI_TARGETLIST_MASK 0xffff 191 #define ICH_SGI_AFFx_MASK 0xff 192 #define ICH_SGI_AFFINITY_LEVEL(x) (16 * (x)) 193 194 struct rdist_region { 195 paddr_t base; 196 paddr_t size; 197 void __iomem *map_base; 198 bool single_rdist; 199 }; 200 201 #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */ 202 203 /* 204 * Local variables: 205 * mode: C 206 * c-file-style: "BSD" 207 * c-basic-offset: 4 208 * indent-tabs-mode: nil 209 * End: 210 */ 211