1 /* 2 * xen/include/asm-arm/scif-uart.h 3 * 4 * Common constant definition between early printk and the UART driver 5 * for the SCIF compatible UART. 6 * 7 * Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com> 8 * Copyright (C) 2014, Globallogic. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #ifndef __ASM_ARM_SCIF_UART_H 22 #define __ASM_ARM_SCIF_UART_H 23 24 #define SCIF_FIFO_MAX_SIZE 16 25 26 /* Register offsets */ 27 #define SCIF_SCSMR (0x00) /* Serial mode register */ 28 #define SCIF_SCBRR (0x04) /* Bit rate register */ 29 #define SCIF_SCSCR (0x08) /* Serial control register */ 30 #define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ 31 #define SCIF_SCFSR (0x10) /* Serial status register */ 32 #define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ 33 #define SCIF_SCFCR (0x18) /* FIFO control register */ 34 #define SCIF_SCFDR (0x1C) /* FIFO data count register */ 35 #define SCIF_SCSPTR (0x20) /* Serial port register */ 36 #define SCIF_SCLSR (0x24) /* Line status register */ 37 #define SCIF_DL (0x30) /* Frequency division register */ 38 #define SCIF_CKS (0x34) /* Clock Select register */ 39 40 /* Serial Control Register (SCSCR) */ 41 #define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */ 42 #define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */ 43 #define SCSCR_TE (1 << 5) /* Transmit Enable */ 44 #define SCSCR_RE (1 << 4) /* Receive Enable */ 45 #define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable */ 46 #define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable */ 47 #define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */ 48 #define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */ 49 50 #define SCSCR_CKE00 (0) 51 #define SCSCR_CKE01 (SCSCR_CKE0) 52 #define SCSCR_CKE10 (SCSCR_CKE1) 53 #define SCSCR_CKE11 (SCSCR_CKE1 | SCSCR_CKE0) 54 55 /* Serial Mode Register (SCSMR) */ 56 #define SCSMR_CHR (1 << 6) /* 7-bit Character Length */ 57 #define SCSMR_PE (1 << 5) /* Parity Enable */ 58 #define SCSMR_ODD (1 << 4) /* Odd Parity */ 59 #define SCSMR_STOP (1 << 3) /* Stop Bit Length */ 60 61 /* Serial Status Register (SCFSR) */ 62 #define SCFSR_ER (1 << 7) /* Receive Error */ 63 #define SCFSR_TEND (1 << 6) /* Transmission End */ 64 #define SCFSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ 65 #define SCFSR_BRK (1 << 4) /* Break Detect */ 66 #define SCFSR_FER (1 << 3) /* Framing Error */ 67 #define SCFSR_PER (1 << 2) /* Parity Error */ 68 #define SCFSR_RDF (1 << 1) /* Receive FIFO Data Full */ 69 #define SCFSR_DR (1 << 0) /* Receive Data Ready */ 70 71 #define SCIF_ERRORS (SCFSR_PER | SCFSR_FER | SCFSR_ER | SCFSR_BRK) 72 73 /* Line Status Register (SCLSR) */ 74 #define SCLSR_TO (1 << 2) /* Timeout */ 75 #define SCLSR_ORER (1 << 0) /* Overrun Error */ 76 77 /* FIFO Control Register (SCFCR) */ 78 #define SCFCR_RTRG1 (1 << 7) /* Receive FIFO Data Count Trigger 1 */ 79 #define SCFCR_RTRG0 (1 << 6) /* Receive FIFO Data Count Trigger 0 */ 80 #define SCFCR_TTRG1 (1 << 5) /* Transmit FIFO Data Count Trigger 1 */ 81 #define SCFCR_TTRG0 (1 << 4) /* Transmit FIFO Data Count Trigger 0 */ 82 #define SCFCR_MCE (1 << 3) /* Modem Control Enable */ 83 #define SCFCR_TFRST (1 << 2) /* Transmit FIFO Data Register Reset */ 84 #define SCFCR_RFRST (1 << 1) /* Receive FIFO Data Register Reset */ 85 #define SCFCR_LOOP (1 << 0) /* Loopback Test */ 86 87 #define SCFCR_RTRG00 (0) 88 #define SCFCR_RTRG01 (SCFCR_RTRG0) 89 #define SCFCR_RTRG10 (SCFCR_RTRG1) 90 #define SCFCR_RTRG11 (SCFCR_RTRG1 | SCFCR_RTRG0) 91 92 #define SCFCR_TTRG00 (0) 93 #define SCFCR_TTRG01 (SCFCR_TTRG0) 94 #define SCFCR_TTRG10 (SCFCR_TTRG1) 95 #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) 96 97 #endif /* __ASM_ARM_SCIF_UART_H */ 98 99 /* 100 * Local variables: 101 * mode: C 102 * c-file-style: "BSD" 103 * c-basic-offset: 4 104 * indent-tabs-mode: nil 105 * End: 106 */ 107