1 #ifndef __ASM_APICDEF_H 2 #define __ASM_APICDEF_H 3 4 /* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 12 13 #define APIC_ID 0x20 14 #define APIC_ID_MASK (0xFFu<<24) 15 #define GET_xAPIC_ID(x) (((x)>>24)&0xFFu) 16 #define SET_xAPIC_ID(x) (((x)<<24)) 17 #define APIC_LVR 0x30 18 #define APIC_LVR_MASK 0xFF00FF 19 #define APIC_LVR_DIRECTED_EOI (1 << 24) 20 #define GET_APIC_VERSION(x) ((x)&0xFF) 21 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF) 22 #define APIC_XAPIC(x) ((x) >= 0x14) 23 #define APIC_TASKPRI 0x80 24 #define APIC_TPRI_MASK 0xFF 25 #define APIC_ARBPRI 0x90 26 #define APIC_ARBPRI_MASK 0xFF 27 #define APIC_PROCPRI 0xA0 28 #define APIC_EOI 0xB0 29 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */ 30 #define APIC_RRR 0xC0 31 #define APIC_LDR 0xD0 32 #define APIC_LDR_MASK (0xFFu<<24) 33 #define GET_xAPIC_LOGICAL_ID(x) (((x)>>24)&0xFF) 34 #define SET_xAPIC_LOGICAL_ID(x) (((x)<<24)) 35 #define APIC_ALL_CPUS 0xFF 36 #define APIC_DFR 0xE0 37 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 38 #define APIC_DFR_FLAT 0xFFFFFFFFul 39 #define APIC_SPIV 0xF0 40 #define APIC_SPIV_FOCUS_DISABLED (1<<9) 41 #define APIC_SPIV_APIC_ENABLED (1<<8) 42 #define APIC_SPIV_DIRECTED_EOI (1<<12) 43 #define APIC_ISR 0x100 44 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 45 #define APIC_TMR 0x180 46 #define APIC_IRR 0x200 47 #define APIC_ESR 0x280 48 #define APIC_ESR_SEND_CS 0x00001 49 #define APIC_ESR_RECV_CS 0x00002 50 #define APIC_ESR_SEND_ACC 0x00004 51 #define APIC_ESR_RECV_ACC 0x00008 52 #define APIC_ESR_SENDILL 0x00020 53 #define APIC_ESR_RECVILL 0x00040 54 #define APIC_ESR_ILLREGA 0x00080 55 #define APIC_ICR 0x300 56 #define APIC_DEST_NOSHORT 0x00000 57 #define APIC_DEST_SELF 0x40000 58 #define APIC_DEST_ALLINC 0x80000 59 #define APIC_DEST_ALLBUT 0xC0000 60 #define APIC_SHORT_MASK 0xC0000 61 #define APIC_ICR_RR_MASK 0x30000 62 #define APIC_ICR_RR_INVALID 0x00000 63 #define APIC_ICR_RR_INPROG 0x10000 64 #define APIC_ICR_RR_VALID 0x20000 65 #define APIC_INT_LEVELTRIG 0x08000 66 #define APIC_INT_ASSERT 0x04000 67 #define APIC_ICR_BUSY 0x01000 68 #define APIC_DEST_MASK 0x00800 69 #define APIC_DEST_LOGICAL 0x00800 70 #define APIC_DEST_PHYSICAL 0x00000 71 #define APIC_DM_FIXED 0x00000 72 #define APIC_DM_LOWEST 0x00100 73 #define APIC_DM_SMI 0x00200 74 #define APIC_DM_REMRD 0x00300 75 #define APIC_DM_NMI 0x00400 76 #define APIC_DM_INIT 0x00500 77 #define APIC_DM_STARTUP 0x00600 78 #define APIC_DM_EXTINT 0x00700 79 #define APIC_VECTOR_MASK 0x000FF 80 #define APIC_ICR2 0x310 81 #define GET_xAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) 82 #define SET_xAPIC_DEST_FIELD(x) ((x)<<24) 83 #define APIC_LVTT 0x320 84 #define APIC_LVTTHMR 0x330 85 #define APIC_LVTPC 0x340 86 #define APIC_LVT0 0x350 87 #define APIC_CMCI 0x2F0 88 89 #define APIC_TIMER_MODE_MASK (0x3<<17) 90 #define APIC_TIMER_MODE_ONESHOT (0x0<<17) 91 #define APIC_TIMER_MODE_PERIODIC (0x1<<17) 92 #define APIC_TIMER_MODE_TSC_DEADLINE (0x2<<17) 93 #define APIC_LVT_MASKED (1<<16) 94 #define APIC_LVT_LEVEL_TRIGGER (1<<15) 95 #define APIC_LVT_REMOTE_IRR (1<<14) 96 #define APIC_INPUT_POLARITY (1<<13) 97 #define APIC_SEND_PENDING (1<<12) 98 #define APIC_MODE_MASK 0x700 99 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) 100 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) 101 #define APIC_MODE_FIXED 0x0 102 #define APIC_MODE_NMI 0x4 103 #define APIC_MODE_EXTINT 0x7 104 #define APIC_LVT1 0x360 105 #define APIC_LVTERR 0x370 106 #define APIC_TMICT 0x380 107 #define APIC_TMCCT 0x390 108 #define APIC_TDCR 0x3E0 109 #define APIC_TDR_DIV_TMBASE (1<<2) 110 #define APIC_TDR_DIV_1 0xB 111 #define APIC_TDR_DIV_2 0x0 112 #define APIC_TDR_DIV_4 0x1 113 #define APIC_TDR_DIV_8 0x2 114 #define APIC_TDR_DIV_16 0x3 115 #define APIC_TDR_DIV_32 0x8 116 #define APIC_TDR_DIV_64 0x9 117 #define APIC_TDR_DIV_128 0xA 118 119 /* Only available in x2APIC mode */ 120 #define APIC_SELF_IPI 0x3F0 121 122 #define APIC_BASE __fix_to_virt(FIX_APIC_BASE) 123 124 /* It's only used in x2APIC mode of an x2APIC unit. */ 125 #define APIC_MSR_BASE 0x800 126 127 #define MAX_IO_APICS 128 128 129 #endif 130