1 /* 2 * Machine dependent access functions for RTC registers. 3 */ 4 #ifndef _ASM_MC146818RTC_H 5 #define _ASM_MC146818RTC_H 6 7 #include <asm/io.h> 8 #include <xen/spinlock.h> 9 10 extern spinlock_t rtc_lock; /* serialize CMOS RAM access */ 11 12 /********************************************************************** 13 * register summary 14 **********************************************************************/ 15 #define RTC_SECONDS 0 16 #define RTC_SECONDS_ALARM 1 17 #define RTC_MINUTES 2 18 #define RTC_MINUTES_ALARM 3 19 #define RTC_HOURS 4 20 #define RTC_HOURS_ALARM 5 21 /* RTC_*_alarm is always true if 2 MSBs are set */ 22 # define RTC_ALARM_DONT_CARE 0xC0 23 24 #define RTC_DAY_OF_WEEK 6 25 #define RTC_DAY_OF_MONTH 7 26 #define RTC_MONTH 8 27 #define RTC_YEAR 9 28 29 /* control registers - Moto names 30 */ 31 #define RTC_REG_A 10 32 #define RTC_REG_B 11 33 #define RTC_REG_C 12 34 #define RTC_REG_D 13 35 36 /********************************************************************** 37 * register details 38 **********************************************************************/ 39 #define RTC_FREQ_SELECT RTC_REG_A 40 41 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 42 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 43 * totalling to a max high interval of 2.228 ms. 44 */ 45 # define RTC_UIP 0x80 46 # define RTC_DIV_CTL 0x70 47 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 48 # define RTC_REF_CLCK_4MHZ 0x00 49 # define RTC_REF_CLCK_1MHZ 0x10 50 # define RTC_REF_CLCK_32KHZ 0x20 51 /* 2 values for divider stage reset, others for "testing purposes only" */ 52 # define RTC_DIV_RESET1 0x60 53 # define RTC_DIV_RESET2 0x70 54 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 55 # define RTC_RATE_SELECT 0x0F 56 57 /**********************************************************************/ 58 #define RTC_CONTROL RTC_REG_B 59 # define RTC_SET 0x80 /* disable updates for clock setting */ 60 # define RTC_PIE 0x40 /* periodic interrupt enable */ 61 # define RTC_AIE 0x20 /* alarm interrupt enable */ 62 # define RTC_UIE 0x10 /* update-finished interrupt enable */ 63 # define RTC_SQWE 0x08 /* enable square-wave output */ 64 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 65 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 66 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 67 68 /**********************************************************************/ 69 #define RTC_INTR_FLAGS RTC_REG_C 70 /* caution - cleared by read */ 71 # define RTC_IRQF 0x80 /* any of the following 3 is active */ 72 # define RTC_PF 0x40 73 # define RTC_AF 0x20 74 # define RTC_UF 0x10 75 76 /**********************************************************************/ 77 #define RTC_VALID RTC_REG_D 78 # define RTC_VRT 0x80 /* valid RAM and time */ 79 /**********************************************************************/ 80 81 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) 82 * determines if the following two #defines are needed 83 */ 84 #ifndef BCD_TO_BIN 85 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) 86 #endif 87 88 #ifndef BIN_TO_BCD 89 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) 90 #endif 91 92 93 #ifndef RTC_PORT 94 #define RTC_PORT(x) (0x70 + (x)) 95 #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ 96 #endif 97 98 /* 99 * The yet supported machines all access the RTC index register via 100 * an ISA port access but the way to access the date register differs ... 101 */ 102 #define CMOS_READ(addr) ({ \ 103 outb_p((addr),RTC_PORT(0)); \ 104 inb_p(RTC_PORT(1)); \ 105 }) 106 #define CMOS_WRITE(val, addr) ({ \ 107 outb_p((addr),RTC_PORT(0)); \ 108 outb_p((val),RTC_PORT(1)); \ 109 }) 110 111 #define RTC_IRQ 8 112 113 #endif /* _ASM_MC146818RTC_H */ 114