1 #include <xen/types.h> 2 #include <public/arch-x86/xen-mca.h> 3 #ifndef _XEN_X86_MCE_H 4 #define _XEN_X86_MCE_H 5 6 /* 7 * Emulate 2 banks for guest 8 * Bank0: reserved for 'bank0 quirk' occur at some very old processors: 9 * 1). Intel cpu whose family-model value < 06-1A; 10 * 2). AMD K7 11 * Bank1: used to transfer error info to guest 12 */ 13 #define GUEST_MC_BANK_NUM 2 14 15 /* Filter MSCOD model specific error code to guest */ 16 #define MCi_STATUS_MSCOD_MASK (~(0xffffULL << 16)) 17 18 /* No mci_ctl since it stick all 1's */ 19 struct vmce_bank { 20 uint64_t mci_status; 21 uint64_t mci_addr; 22 uint64_t mci_misc; 23 uint64_t mci_ctl2; 24 }; 25 26 /* No mcg_ctl since it not expose to guest */ 27 struct vmce { 28 uint64_t mcg_cap; 29 uint64_t mcg_status; 30 uint64_t mcg_ext_ctl; 31 spinlock_t lock; 32 struct vmce_bank bank[GUEST_MC_BANK_NUM]; 33 }; 34 35 /* Guest vMCE MSRs virtualization */ 36 extern void vmce_init_vcpu(struct vcpu *); 37 extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *); 38 extern int vmce_wrmsr(uint32_t msr, uint64_t val); 39 extern int vmce_rdmsr(uint32_t msr, uint64_t *val); 40 extern bool vmce_has_lmce(const struct vcpu *v); 41 extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap); 42 43 extern unsigned int nr_mce_banks; 44 45 #endif 46