Lines Matching refs:cycles
69 Active bank a to active bank b in terms of number of clock cycles.
76 Internal WRITE-to-READ command delay in terms of number of clock cycles.
84 cycles. Obtained from device datasheet.
91 cycles. Obtained from device datasheet.
98 of clock cycles. Obtained from device datasheet.
104 Row precharge time (all banks) in terms of number of clock cycles.
111 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
118 WRITE recovery time in terms of number of clock cycles. Obtained from
125 Row active time in terms of number of clock cycles. Obtained from device
133 SELF REFRESH) in terms of number of clock cycles. Obtained from device
140 Four-bank activate window in terms of number of clock cycles. Obtained