Lines Matching refs:delay
34 # They are used to delay the data valid window, and align the window to
35 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
38 cdns,phy-input-delay-sd-highspeed:
39 description: Value of the delay in the input path for SD high-speed timing
44 cdns,phy-input-delay-legacy:
45 description: Value of the delay in the input path for legacy timing
50 cdns,phy-input-delay-sd-uhs-sdr12:
51 description: Value of the delay in the input path for SD UHS SDR12 timing
56 cdns,phy-input-delay-sd-uhs-sdr25:
57 description: Value of the delay in the input path for SD UHS SDR25 timing
62 cdns,phy-input-delay-sd-uhs-sdr50:
63 description: Value of the delay in the input path for SD UHS SDR50 timing
68 cdns,phy-input-delay-sd-uhs-ddr50:
69 description: Value of the delay in the input path for SD UHS DDR50 timing
74 cdns,phy-input-delay-mmc-highspeed:
75 description: Value of the delay in the input path for MMC high-speed timing
80 cdns,phy-input-delay-mmc-ddr:
81 description: Value of the delay in the input path for eMMC high-speed DDR timing
84 # Each delay property represents the fraction of the clock period.
85 # The approximate delay value will be
86 # (<delay property value>/128)*sdmclk_clock_period.
91 cdns,phy-dll-delay-sdclk:
93 Value of the delay introduced on the sdclk output for all modes except
99 cdns,phy-dll-delay-sdclk-hsmmc:
101 Value of the delay introduced on the sdclk output for HS200, HS400 and
107 cdns,phy-dll-delay-strobe:
109 Value of the delay introduced on the dat_strobe input used in
134 cdns,phy-dll-delay-sdclk = <0>;