Lines Matching refs:mcr
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
149 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
734 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
735 mcr p15, 0, r0, c6, c7, 1
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
747 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
749 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
755 mcr p15, 0, r0, c1, c0, 0 @ write control reg
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
759 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
764 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
767 mcr p15, 0, r0, c2, c0, 0 @ cache on
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
784 mcr p15, 0, r0, c1, c0, 0 @ write control reg
787 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
843 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
849 mcr p15, 7, r0, c15, c0, 0
858 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
859 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
866 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
879 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
901 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c1, c0, 0 @ load control register
905 mcr p15, 0, r0, c7, c5, 4 @ ISB
913 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
914 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
915 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
920 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
929 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
930 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
933 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
1165 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1167 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1168 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1175 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1177 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1184 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1186 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1187 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1198 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1201 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1203 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1204 mcr p15, 0, r0, c7, c10, 4 @ DSB
1205 mcr p15, 0, r0, c7, c5, 4 @ ISB
1230 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1233 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1248 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1249 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1250 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1257 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1259 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1270 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1280 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1284 mcr p15, 0, r10, c7, c10, 4 @ DSB
1285 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1286 mcr p15, 0, r10, c7, c10, 4 @ DSB
1287 mcr p15, 0, r10, c7, c5, 4 @ ISB
1295 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1296 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1328 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1329 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1330 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1338 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1451 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR