Lines Matching refs:x1
42 mrs x1, id_aa64dfr0_el1
43 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
52 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
68 ubfx x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
85 mrs x1, id_aa64mmfr1_el1
86 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
121 mrs x1, mpidr_el1
123 msr vmpidr_el2, x1
134 mrs x1, id_aa64pfr0_el1
135 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
136 cbz x1, .Lskip_sve_\@
141 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
142 msr_s SYS_ZCR_EL2, x1 // length for EL1.
148 mrs x1, id_aa64mmfr0_el1
149 ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
150 cbz x1, .Lskip_fgt_\@
153 mrs x1, id_aa64dfr0_el1
154 ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
155 cmp x1, #3
167 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
168 ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
169 cbz x1, .Lskip_fgt_\@