Lines Matching refs:iir
438 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned()
467 switch (MAJOR_OP(regs->iir)) in handle_unaligned()
472 if (regs->iir&0x20) in handle_unaligned()
475 if (regs->iir&0x1000) /* short loads */ in handle_unaligned()
476 if (regs->iir&0x200) in handle_unaligned()
477 newbase += IM5_3(regs->iir); in handle_unaligned()
479 newbase += IM5_2(regs->iir); in handle_unaligned()
480 else if (regs->iir&0x2000) /* scaled indexed */ in handle_unaligned()
483 switch (regs->iir & OPCODE1_MASK) in handle_unaligned()
493 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; in handle_unaligned()
495 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); in handle_unaligned()
501 newbase += IM14(regs->iir); in handle_unaligned()
505 if (regs->iir&8) in handle_unaligned()
508 newbase += IM14(regs->iir&~0xe); in handle_unaligned()
514 newbase += IM14(regs->iir&6); in handle_unaligned()
518 if (regs->iir&4) in handle_unaligned()
521 newbase += IM14(regs->iir&~4); in handle_unaligned()
527 switch (regs->iir & OPCODE1_MASK) in handle_unaligned()
531 ret = emulate_ldh(regs, R3(regs->iir)); in handle_unaligned()
538 ret = emulate_ldw(regs, R3(regs->iir),0); in handle_unaligned()
542 ret = emulate_sth(regs, R2(regs->iir)); in handle_unaligned()
547 ret = emulate_stw(regs, R2(regs->iir),0); in handle_unaligned()
555 ret = emulate_ldd(regs, R3(regs->iir),0); in handle_unaligned()
560 ret = emulate_std(regs, R2(regs->iir),0); in handle_unaligned()
569 ret = emulate_ldw(regs,FR3(regs->iir),1); in handle_unaligned()
575 ret = emulate_ldd(regs,R3(regs->iir),1); in handle_unaligned()
583 ret = emulate_stw(regs,FR3(regs->iir),1); in handle_unaligned()
589 ret = emulate_std(regs,R3(regs->iir),1); in handle_unaligned()
600 switch (regs->iir & OPCODE2_MASK) in handle_unaligned()
604 ret = emulate_ldd(regs,R2(regs->iir),1); in handle_unaligned()
608 ret = emulate_std(regs, R2(regs->iir),1); in handle_unaligned()
611 ret = emulate_ldd(regs, R2(regs->iir),0); in handle_unaligned()
614 ret = emulate_std(regs, R2(regs->iir),0); in handle_unaligned()
618 switch (regs->iir & OPCODE3_MASK) in handle_unaligned()
622 ret = emulate_ldw(regs, R2(regs->iir),0); in handle_unaligned()
625 ret = emulate_ldw(regs, R2(regs->iir),1); in handle_unaligned()
630 ret = emulate_stw(regs, R2(regs->iir),1); in handle_unaligned()
633 ret = emulate_stw(regs, R2(regs->iir),0); in handle_unaligned()
636 switch (regs->iir & OPCODE4_MASK) in handle_unaligned()
639 ret = emulate_ldh(regs, R2(regs->iir)); in handle_unaligned()
643 ret = emulate_ldw(regs, R2(regs->iir),0); in handle_unaligned()
646 ret = emulate_sth(regs, R2(regs->iir)); in handle_unaligned()
650 ret = emulate_stw(regs, R2(regs->iir),0); in handle_unaligned()
654 if (ret == 0 && modify && R1(regs->iir)) in handle_unaligned()
655 regs->gr[R1(regs->iir)] = newbase; in handle_unaligned()
659 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); in handle_unaligned()
709 switch (regs->iir & OPCODE1_MASK) { in check_unaligned()
727 switch (regs->iir & OPCODE4_MASK) { in check_unaligned()