Lines Matching refs:event
11 PMU_FORMAT_ATTR(event, "config:0-49");
45 static inline bool event_is_fab_match(u64 event) in event_is_fab_match() argument
48 event &= 0xff0fe; in event_is_fab_match()
51 return (event == 0x30056 || event == 0x4f052); in event_is_fab_match()
54 static bool is_event_valid(u64 event) in is_event_valid() argument
63 return !(event & ~valid_mask); in is_event_valid()
66 static inline bool is_event_marked(u64 event) in is_event_marked() argument
68 if (event & EVENT_IS_MARKED) in is_event_marked()
74 static unsigned long sdar_mod_val(u64 event) in sdar_mod_val() argument
77 return p10_SDAR_MODE(event); in sdar_mod_val()
79 return p9_SDAR_MODE(event); in sdar_mod_val()
82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) in mmcra_sdar_mode() argument
101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) in mmcra_sdar_mode()
103 else if (sdar_mod_val(event)) in mmcra_sdar_mode()
104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT; in mmcra_sdar_mode()
164 static unsigned long combine_from_event(u64 event) in combine_from_event() argument
167 return p9_EVENT_COMBINE(event); in combine_from_event()
169 return EVENT_COMBINE(event); in combine_from_event()
180 static inline bool event_is_threshold(u64 event) in event_is_threshold() argument
182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; in event_is_threshold()
185 static bool is_thresh_cmp_valid(u64 event) in is_thresh_cmp_valid() argument
190 return p10_thresh_cmp_val(event) != 0; in is_thresh_cmp_valid()
197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; in is_thresh_cmp_valid()
206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event) in dc_ic_rld_quad_l1_sel() argument
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; in dc_ic_rld_quad_l1_sel()
371 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1) in isa207_get_constraint() argument
378 if (!is_event_valid(event)) in isa207_get_constraint()
381 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; in isa207_get_constraint()
382 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; in isa207_get_constraint()
384 cache = (event >> EVENT_CACHE_SEL_SHIFT) & in isa207_get_constraint()
387 cache = (event >> EVENT_CACHE_SEL_SHIFT) & in isa207_get_constraint()
389 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; in isa207_get_constraint()
398 base_event = event & ~EVENT_LINUX_MASK; in isa207_get_constraint()
432 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); in isa207_get_constraint()
436 value |= CNST_CACHE_GROUP_VAL(event & 0xff); in isa207_get_constraint()
454 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { in isa207_get_constraint()
461 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT); in isa207_get_constraint()
464 if (is_event_marked(event)) { in isa207_get_constraint()
466 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); in isa207_get_constraint()
470 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) { in isa207_get_constraint()
472 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); in isa207_get_constraint()
477 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { in isa207_get_constraint()
479 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); in isa207_get_constraint()
486 if (event_is_fab_match(event)) { in isa207_get_constraint()
488 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); in isa207_get_constraint()
490 if (!is_thresh_cmp_valid(event)) in isa207_get_constraint()
494 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); in isa207_get_constraint()
503 if (event & EVENT_WANTS_BHRB) { in isa207_get_constraint()
509 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); in isa207_get_constraint()
526 int isa207_compute_mmcr(u64 event[], int n_ev, in isa207_compute_mmcr() argument
539 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; in isa207_compute_mmcr()
555 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; in isa207_compute_mmcr()
556 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; in isa207_compute_mmcr()
557 combine = combine_from_event(event[i]); in isa207_compute_mmcr()
558 psel = event[i] & EVENT_PSEL_MASK; in isa207_compute_mmcr()
576 mmcra_sdar_mode(event[i], &mmcra); in isa207_compute_mmcr()
579 cache = dc_ic_rld_quad_l1_sel(event[i]); in isa207_compute_mmcr()
582 if (event[i] & EVENT_IS_L1) { in isa207_compute_mmcr()
583 cache = dc_ic_rld_quad_l1_sel(event[i]); in isa207_compute_mmcr()
590 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) & in isa207_compute_mmcr()
595 if (is_event_marked(event[i])) { in isa207_compute_mmcr()
598 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; in isa207_compute_mmcr()
609 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { in isa207_compute_mmcr()
610 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & in isa207_compute_mmcr()
613 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; in isa207_compute_mmcr()
615 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; in isa207_compute_mmcr()
618 val = (event[i] >> EVENT_THR_CMP_SHIFT) & in isa207_compute_mmcr()
629 val = (event[i] >> p10_L2L3_EVENT_SHIFT) & in isa207_compute_mmcr()
634 if (event[i] & EVENT_WANTS_BHRB) { in isa207_compute_mmcr()
635 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; in isa207_compute_mmcr()
641 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB))) in isa207_compute_mmcr()
659 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) & in isa207_compute_mmcr()
704 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) in find_alternative() argument
709 if (event < ev_alt[i][0]) in find_alternative()
713 if (event == ev_alt[i][j]) in find_alternative()
720 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, in isa207_get_alternatives() argument
726 alt[num_alt++] = event; in isa207_get_alternatives()
727 i = find_alternative(event, ev_alt, size); in isa207_get_alternatives()
732 if (alt_event && alt_event != event) in isa207_get_alternatives()
768 u64 event = ev->attr.config; in isa3XX_check_attr_config() local
770 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; in isa3XX_check_attr_config()
800 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; in isa3XX_check_attr_config()